On 09/03/2022 19:26, Darren Hart wrote:
> On Wed, Mar 09, 2022 at 01:50:07PM +0100, Dietmar Eggemann wrote:
>> On 08/03/2022 18:49, Darren Hart wrote:
>>> On Tue, Mar 08, 2022 at 05:03:07PM +0100, Dietmar Eggemann wrote:
>>>> On 08/03/2022 12:04, Vincent Guittot wrote:
>>>>> On Tue, 8 Mar 2022 at 11:30, Will Deacon <will@xxxxxxxxxx> wrote:
[...]
>>>> I do not have any better idea than this tweak here either in case the
>>>> platform can't provide a cleaner setup.
>>>
>>> I'd argue The platform is describing itself accurately in ACPI PPTT
>>> terms. The topology doesn't fit nicely within the kernel abstractions
>>> today. This is an area where I hope to continue to improve things going
>>> forward.
>>
>> I see. And I assume lying about SCU/LLC boundaries in ACPI is not an
>> option since it messes up /sys/devices/system/cpu/cpu0/cache/index*/.
>>
>> [...]
>
> I'm not aware of a way to accurately describe the SCU topology in the PPTT, and
> the risk we run with lying about LLC topology is that lie has to be comprehended
> by all OSes and not conflict with other lies people may ask for. In general, I
> think it is preferable and more maintainable to describe the topology as
> accurately and honestly as we can within the existing platform mechanisms (PPTT,
> HMAT, etc) and work on the higher level abstractions to accommodate a broader
> set of topologies as they emerge (as well as working to more fully describe the
> topology with new platform level mechanisms as needed).
>
> As I mentioned, I intend to continue looking in to how to improve the current
> abstractions. For now, it sounds like we have agreement that this patch can be
> merged to address the BUG?
What about swapping the CLS and MC cpumasks for such a machine? This
would avoid that the task scheduler has to deal with a system which has
CLS but no MC. We essentially promote the CLS cpumask up to MC in this
case.
cat /sys/kernel/debug/sched/domains/cpu0/domain*/name
MC
^^
DIE
NUMA
cat /sys/kernel/debug/sched/domains/cpu0# cat domain*/flags
SD_BALANCE_NEWIDLE SD_BALANCE_EXEC SD_BALANCE_FORK SD_WAKE_AFFINE SD_SHARE_PKG_RESOURCES SD_PREFER_SIBLING
^^^^^^^^^^^^^^^^^^^^^^
SD_BALANCE_NEWIDLE SD_BALANCE_EXEC SD_BALANCE_FORK SD_WAKE_AFFINE SD_PREFER_SIBLING
SD_BALANCE_NEWIDLE SD_BALANCE_EXEC SD_BALANCE_FORK SD_WAKE_AFFINE SD_SERIALIZE SD_OVERLAP SD_NUMA
Only very lightly tested on Altra and Juno-r0 (DT).
--->8---
