On Sat, Mar 05, 2022 at 09:09:45PM +0100, gregkh@xxxxxxxxxxxxxxxxxxx wrote:
>
> The patch below does not apply to the 5.15-stable tree.
> If someone wants it applied there, or to any other stable or longterm
> tree, then please email the backport, including the original git commit
> id to <stable@xxxxxxxxxxxxxxx>.
>
> thanks,
>
> greg k-h
Hello Stable (Greg),
Original commit in Linus tree:
74583f1b92cb3bbba1a3741cea237545c56f506c
Attaching a patch that will apply for 5.15 and 5.16.
Kind regards,
Niklas
>
> ------------------ original commit in Linus's tree ------------------
>
> From 74583f1b92cb3bbba1a3741cea237545c56f506c Mon Sep 17 00:00:00 2001
> From: Niklas Cassel <niklas.cassel@xxxxxxx>
> Date: Tue, 1 Mar 2022 00:44:18 +0000
> Subject: [PATCH] riscv: dts: k210: fix broken IRQs on hart1
>
> Commit 67d96729a9e7 ("riscv: Update Canaan Kendryte K210 device tree")
> incorrectly removed two entries from the PLIC interrupt-controller node's
> interrupts-extended property.
>
> The PLIC driver cannot know the mapping between hart contexts and hart ids,
> so this information has to be provided by device tree, as specified by the
> PLIC device tree binding.
>
> The PLIC driver uses the interrupts-extended property, and initializes the
> hart context registers in the exact same order as provided by the
> interrupts-extended property.
>
> In other words, if we don't specify the S-mode interrupts, the PLIC driver
> will simply initialize the hart0 S-mode hart context with the hart1 M-mode
> configuration. It is therefore essential to specify the S-mode IRQs even
> though the system itself will only ever be running in M-mode.
>
> Re-add the S-mode interrupts, so that we get working IRQs on hart1 again.
>
> Cc: <stable@xxxxxxxxxxxxxxx>
> Fixes: 67d96729a9e7 ("riscv: Update Canaan Kendryte K210 device tree")
> Signed-off-by: Niklas Cassel <niklas.cassel@xxxxxxx>
> Signed-off-by: Palmer Dabbelt <palmer@xxxxxxxxxxxx>
>
> diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi
> index 56f57118c633..44d338514761 100644
> --- a/arch/riscv/boot/dts/canaan/k210.dtsi
> +++ b/arch/riscv/boot/dts/canaan/k210.dtsi
> @@ -113,7 +113,8 @@ plic0: interrupt-controller@c000000 {
> compatible = "canaan,k210-plic", "sifive,plic-1.0.0";
> reg = <0xC000000 0x4000000>;
> interrupt-controller;
> - interrupts-extended = <&cpu0_intc 11>, <&cpu1_intc 11>;
> + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
> + <&cpu1_intc 11>, <&cpu1_intc 9>;
> riscv,ndev = <65>;
> };
>
>
From 74583f1b92cb3bbba1a3741cea237545c56f506c Mon Sep 17 00:00:00 2001
From: Niklas Cassel <niklas.cassel@xxxxxxx>
Date: Tue, 1 Mar 2022 00:44:18 +0000
Subject: [PATCH] riscv: dts: k210: fix broken IRQs on hart1
commit 74583f1b92cb3bbba1a3741cea237545c56f506c upstream.
Commit 67d96729a9e7 ("riscv: Update Canaan Kendryte K210 device tree")
incorrectly removed two entries from the PLIC interrupt-controller node's
interrupts-extended property.
The PLIC driver cannot know the mapping between hart contexts and hart ids,
so this information has to be provided by device tree, as specified by the
PLIC device tree binding.
The PLIC driver uses the interrupts-extended property, and initializes the
hart context registers in the exact same order as provided by the
interrupts-extended property.
In other words, if we don't specify the S-mode interrupts, the PLIC driver
will simply initialize the hart0 S-mode hart context with the hart1 M-mode
configuration. It is therefore essential to specify the S-mode IRQs even
though the system itself will only ever be running in M-mode.
Re-add the S-mode interrupts, so that we get working IRQs on hart1 again.
Cc: <stable@xxxxxxxxxxxxxxx>
Fixes: 67d96729a9e7 ("riscv: Update Canaan Kendryte K210 device tree")
Signed-off-by: Niklas Cassel <niklas.cassel@xxxxxxx>
Signed-off-by: Palmer Dabbelt <palmer@xxxxxxxxxxxx>
---
arch/riscv/boot/dts/canaan/k210.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi
index 56f57118c633..44d338514761 100644
--- a/arch/riscv/boot/dts/canaan/k210.dtsi
+++ b/arch/riscv/boot/dts/canaan/k210.dtsi
@@ -113,7 +113,8 @@ plic0: interrupt-controller@c000000 {
compatible = "canaan,k210-plic", "sifive,plic-1.0.0";
reg = <0xC000000 0x4000000>;
interrupt-controller;
- interrupts-extended = <&cpu0_intc 11 &cpu1_intc 11>;
+ interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
+ <&cpu1_intc 11>, <&cpu1_intc 9>;
riscv,ndev = <65>;
};
--
2.35.1
