On 15.02.2022 17:31, Borislav Petkov wrote:
On Tue, Feb 15, 2022 at 04:11:03AM -0800, Pawan Gupta wrote:
That is exactly what this patch is fixing. Please let me know if you
have any questions.
Just one: does the explanation I've written for this mess, sound about
right?
I admit it has gotten complicated with so many bits associated with TSX.
Your explanation is accurate. I just have a small suggestion below.
+/*
+ * Disabling TSX is not a trivial business.
+ *
+ * First of all, there's a CPUID bit: X86_FEATURE_RTM_ALWAYS_ABORT
+ * which says that TSX is practically disabled (all transactions are
+ * aborted by default). When that bit is set, the kernel unconditionally
+ * disables TSX.
+ *
+ * In order to do that, however, it needs to dance a bit:
+ *
+ * 1. The first method to disable it is through MSR_TSX_FORCE_ABORT and
+ * the MSR is present only when *two* CPUID bits are set:
s/MSR/MSR bit MSR_TFA_TSX_CPUID_CLEAR/
Thanks,
Pawan
