On Mon, Jan 31, 2022 at 09:43:33AM -0800, Tony Luck wrote:
> commit e464121f2d40eabc7d11823fb26db807ce945df4 upstream
>
> Missed adding the Icelake-D CPU to the list. It uses the same MSRs
> to control and read the inventory number as all the other models.
>
> Fixes: dc6b025de95b ("x86/mce: Add Xeon Icelake to list of CPUs that support PPIN")
> Reported-by: Ailin Xu <ailin.xu@xxxxxxxxx>
> Signed-off-by: Tony Luck <tony.luck@xxxxxxxxx>
> Signed-off-by: Borislav Petkov <bp@xxxxxxx>
> Cc: <stable@xxxxxxxxxxxxxxx>
> Link: https://lore.kernel.org/r/20220121174743.1875294-2-tony.luck@xxxxxxxxx
> ---
> arch/x86/kernel/cpu/mce/intel.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c
> index 7cf08c1f082e..886d4648c9dd 100644
> --- a/arch/x86/kernel/cpu/mce/intel.c
> +++ b/arch/x86/kernel/cpu/mce/intel.c
> @@ -486,6 +486,7 @@ static void intel_ppin_init(struct cpuinfo_x86 *c)
> case INTEL_FAM6_BROADWELL_X:
> case INTEL_FAM6_SKYLAKE_X:
> case INTEL_FAM6_ICELAKE_X:
> + case INTEL_FAM6_ICELAKE_D:
> case INTEL_FAM6_SAPPHIRERAPIDS_X:
> case INTEL_FAM6_XEON_PHI_KNL:
> case INTEL_FAM6_XEON_PHI_KNM:
> --
> 2.31.1
>
Both now queued up, thanks!
greg k-h
