>From 72a73811c4bd53e0ec8284c12180068468d7c733 Mon Sep 17 00:00:00 2001 From: Tony Luck <tony.luck@xxxxxxxxx> Date: Mon, 31 Jan 2022 09:00:41 -0800 Subject: [PATCH] x86/cpu: Add Sapphire Rapids and Icelake-D to list of CPUs that support PPIN commit a331f5fdd36dba1ffb0239a4dfaaf1df91ff1aab upstream commit e464121f2d40eabc7d11823fb26db807ce945df4 upstream Add Sapphire Rapids and Icelake-D to list of CPUs that support PPIN Signed-off-by: Tony Luck <tony.luck@xxxxxxxxx> --- Failed to backport because the sapphire rapids CPU model number patch had not been backported. Bundled both together here. But if that breaks stable rules or scripts, I can redo as two patches one for each upstream commit. arch/x86/kernel/cpu/mce/intel.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c index 2577d7875781..886d4648c9dd 100644 --- a/arch/x86/kernel/cpu/mce/intel.c +++ b/arch/x86/kernel/cpu/mce/intel.c @@ -486,6 +486,8 @@ static void intel_ppin_init(struct cpuinfo_x86 *c) case INTEL_FAM6_BROADWELL_X: case INTEL_FAM6_SKYLAKE_X: case INTEL_FAM6_ICELAKE_X: + case INTEL_FAM6_ICELAKE_D: + case INTEL_FAM6_SAPPHIRERAPIDS_X: case INTEL_FAM6_XEON_PHI_KNL: case INTEL_FAM6_XEON_PHI_KNM: -- 2.31.1
