On Sat, 2022-01-29 at 17:24 +0100, gregkh@xxxxxxxxxxxxxxxxxxx wrote: > This is a note to let you know that I've just added the patch titled > > usb: dwc3: xilinx: Skip resets and USB3 register settings for USB2.0 mode > > to the 5.16-stable tree which can be found at: > > https://urldefense.com/v3/__http://www.kernel.org/git/?p=linux*kernel*git*stable*stable-queue.git;a=summary__;Ly8vLw!!IOGos0k!zf9QJvY84EtqUpdi6VflkIp1CJqnnCaQoiGGvZ8KORysjiM44hQecYjVySxsuD6OjZA$ > > > The filename of the patch is: > usb-dwc3-xilinx-skip-resets-and-usb3-register-settings-for-usb2.0- > mode.patch > and it can be found in the queue-5.16 subdirectory. > > If you, or anyone else, feels it should not be added to the stable tree, > please let <stable@xxxxxxxxxxxxxxx> know about it. Hi Greg, This patch should likely only go into stable along with the follow-up patch I posted (or something equivalent): https://patchwork.kernel.org/project/linux-usb/patch/20220127221500.177021-1-robert.hancock@xxxxxxxxxx/ Otherwise it will cause a regression. > > > From 9678f3361afc27a3124cd2824aec0227739986fb Mon Sep 17 00:00:00 2001 > From: Robert Hancock <robert.hancock@xxxxxxxxxx> > Date: Tue, 25 Jan 2022 18:02:50 -0600 > Subject: usb: dwc3: xilinx: Skip resets and USB3 register settings for USB2.0 > mode > > From: Robert Hancock <robert.hancock@xxxxxxxxxx> > > commit 9678f3361afc27a3124cd2824aec0227739986fb upstream. > > It appears that the PIPE clock should not be selected when only USB 2.0 > is being used in the design and no USB 3.0 reference clock is used. > Also, the core resets are not required if a USB3 PHY is not in use, and > will break things if USB3 is actually used but the PHY entry is not > listed in the device tree. > > Skip core resets and register settings that are only required for > USB3 mode when no USB3 PHY is specified in the device tree. > > Fixes: 84770f028fab ("usb: dwc3: Add driver for Xilinx platforms") > Cc: stable <stable@xxxxxxxxxxxxxxx> > Signed-off-by: Robert Hancock <robert.hancock@xxxxxxxxxx> > Link: > https://urldefense.com/v3/__https://lore.kernel.org/r/20220126000253.1586760-2-robert.hancock@calian.com__;!!IOGos0k!zf9QJvY84EtqUpdi6VflkIp1CJqnnCaQoiGGvZ8KORysjiM44hQecYjVySxsMI6yBj4$ > > Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx> > --- > drivers/usb/dwc3/dwc3-xilinx.c | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > --- a/drivers/usb/dwc3/dwc3-xilinx.c > +++ b/drivers/usb/dwc3/dwc3-xilinx.c > @@ -110,6 +110,18 @@ static int dwc3_xlnx_init_zynqmp(struct > usb3_phy = NULL; > } > > + /* > + * The following core resets are not required unless a USB3 PHY > + * is used, and the subsequent register settings are not required > + * unless a core reset is performed (they should be set properly > + * by the first-stage boot loader, but may be reverted by a core > + * reset). They may also break the configuration if USB3 is actually > + * in use but the usb3-phy entry is missing from the device tree. > + * Therefore, skip these operations in this case. > + */ > + if (!usb3_phy) > + goto skip_usb3_phy; > + > crst = devm_reset_control_get_exclusive(dev, "usb_crst"); > if (IS_ERR(crst)) { > ret = PTR_ERR(crst); > @@ -188,6 +200,7 @@ static int dwc3_xlnx_init_zynqmp(struct > goto err; > } > > +skip_usb3_phy: > /* > * This routes the USB DMA traffic to go through FPD path instead > * of reaching DDR directly. This traffic routing is needed to > > > Patches currently in stable-queue which might be from > robert.hancock@xxxxxxxxxx are > > queue-5.16/serial-8250-of-fix-mapped-region-size-when-using-reg-offset- > property.patch > queue-5.16/usb-dwc3-xilinx-skip-resets-and-usb3-register-settings-for-usb2.0- > mode.patch > queue-5.16/usb-dwc3-xilinx-fix-error-handling-when-getting-usb3-phy.patch
