[Public]
> -----Original Message-----
> From: Limonciello, Mario <Mario.Limonciello@xxxxxxx>
> Sent: Tuesday, January 25, 2022 09:21
> To: stable@xxxxxxxxxxxxxxx
> Cc: Deucher, Alexander <Alexander.Deucher@xxxxxxx>; Wentland, Harry
> <Harry.Wentland@xxxxxxx>; Limonciello, Mario
> <Mario.Limonciello@xxxxxxx>
> Subject: [PATCH] drm/amdgpu: Use correct VIEWPORT_DIMENSION for DCN2
>
> For some reason this file isn't using the appropriate register
> headers for DCN headers, which means that on DCN2 we're getting
> the VIEWPORT_DIMENSION offset wrong.
>
> This means that we're not correctly carving out the framebuffer
> memory correctly for a framebuffer allocated by EFI and
> therefore see corruption when loading amdgpu before the display
> driver takes over control of the framebuffer scanout.
>
> Fix this by checking the DCE_HWIP and picking the correct offset
> accordingly.
>
> Long-term we should expose this info from DC as GMC shouldn't
> need to know about DCN registers.
>
> Signed-off-by: Mario Limonciello <mario.limonciello@xxxxxxx>
> (cherry picked from commit dc5d4aff2e99c312df8abbe1ee9a731d2913bc1b)
> ---
> This is backported from 5.17-rc1, but doesn't backport cleanly because
> v5.16 changed to IP version harvesting for ASIC detection. 5.15.y doesn't
> have this.
> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 14 +++++++++++++-
> 1 file changed, 13 insertions(+), 1 deletion(-)
One more comment - dc5d4aff2e99c3 backports cleanly to 5.16.y.
So it should just be a straightforward cherry-pick in 5.16.y, this special
modification only for 5.15.y.
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index 5551359d5dfd..a4adbbf3acab 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -72,6 +72,9 @@
> #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0
> 0x049d
> #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_BASE_IDX
> 2
>
> +#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2
> 0x05ea
> +#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2_BASE_IDX
> 2
> +
>
> static const char *gfxhub_client_ids[] = {
> "CB",
> @@ -1103,6 +1106,8 @@ static unsigned gmc_v9_0_get_vbios_fb_size(struct
> amdgpu_device *adev)
> u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
> unsigned size;
>
> + /* TODO move to DC so GMC doesn't need to hard-code DCN registers
> */
> +
> if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL,
> D1VGA_MODE_ENABLE)) {
> size = AMDGPU_VBIOS_VGA_ALLOCATION;
> } else {
> @@ -1110,7 +1115,6 @@ static unsigned gmc_v9_0_get_vbios_fb_size(struct
> amdgpu_device *adev)
>
> switch (adev->asic_type) {
> case CHIP_RAVEN:
> - case CHIP_RENOIR:
> viewport = RREG32_SOC15(DCE, 0,
> mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
> size = (REG_GET_FIELD(viewport,
>
> HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
> @@ -1118,6 +1122,14 @@ static unsigned gmc_v9_0_get_vbios_fb_size(struct
> amdgpu_device *adev)
>
> HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) *
> 4);
> break;
> + case CHIP_RENOIR:
> + viewport = RREG32_SOC15(DCE, 0,
> mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2);
> + size = (REG_GET_FIELD(viewport,
> +
> HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
> + REG_GET_FIELD(viewport,
> +
> HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) *
> + 4);
> + break;
> case CHIP_VEGA10:
> case CHIP_VEGA12:
> case CHIP_VEGA20:
> --
> 2.25.1
