[AMD Official Use Only]
> -----Original Message-----
> From: Limonciello, Mario <Mario.Limonciello@xxxxxxx>
> Sent: Monday, November 29, 2021 1:25 PM
> To: stable@xxxxxxxxxxxxxxx
> Cc: Deucher, Alexander <Alexander.Deucher@xxxxxxx>; Tuikov, Luben
> <Luben.Tuikov@xxxxxxx>; Limonciello, Mario
> <Mario.Limonciello@xxxxxxx>
> Subject: [PATCH] drm/amdgpu/gfx10: add wraparound gpu counter check
> for APUs as well
>
> From: Alex Deucher <alexander.deucher@xxxxxxx>
>
> commit 244ee398855d ("drm/amdgpu/gfx10: add wraparound gpu counter
> check for APUs as well")
>
> Apply the same check we do for dGPUs for APUs as well.
>
> Acked-by: Luben Tuikov <luben.tuikov@xxxxxxx>
> Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx>
> Signed-off-by: Mario Limnonciello <mario.limonciello@xxxxxxx>
I just send these out earlier today and Greg applied them. I forgot to cc you.
Alex
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 15 +++++++++++++--
> 1 file changed, 13 insertions(+), 2 deletions(-)
>
> Modified to take use ASIC IDs rather than IP version checking Please apply to
> both 5.14.y and 5.15.y.
>
> When applying to 5.14.y this also has a dependency of:
> commit 5af4438f1e83 ("drm/amdgpu: Read clock counter via MMIO to
> reduce delay (v5)") If necessary I can send that separately.
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index 16dbe593cba2..970d59a21005 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -7729,8 +7729,19 @@ static uint64_t
> gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
> switch (adev->asic_type) {
> case CHIP_VANGOGH:
> case CHIP_YELLOW_CARP:
> - clock = (uint64_t)RREG32_SOC15(SMUIO, 0,
> mmGOLDEN_TSC_COUNT_LOWER_Vangogh) |
> - ((uint64_t)RREG32_SOC15(SMUIO, 0,
> mmGOLDEN_TSC_COUNT_UPPER_Vangogh) << 32ULL);
> + preempt_disable();
> + clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0,
> mmGOLDEN_TSC_COUNT_UPPER_Vangogh);
> + clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0,
> mmGOLDEN_TSC_COUNT_LOWER_Vangogh);
> + hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0,
> mmGOLDEN_TSC_COUNT_UPPER_Vangogh);
> + /* The SMUIO TSC clock frequency is 100MHz, which sets 32-
> bit carry over
> + * roughly every 42 seconds.
> + */
> + if (hi_check != clock_hi) {
> + clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0,
> mmGOLDEN_TSC_COUNT_LOWER_Vangogh);
> + clock_hi = hi_check;
> + }
> + preempt_enable();
> + clock = clock_lo | (clock_hi << 32ULL);
> break;
> default:
> preempt_disable();
> --
> 2.25.1
