On Sunday 14 November 2021 15:13:31 gregkh@xxxxxxxxxxxxxxxxxxx wrote: > The patch below does not apply to the 5.15-stable tree. > If someone wants it applied there, or to any other stable or longterm > tree, then please email the backport, including the original git commit > id to <stable@xxxxxxxxxxxxxxx>. > > thanks, > > greg k-h Hello Greg! Following patch is needed for PCI_EXP_DEVCTL_PAYLOAD_512B macro: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=460275f124fb072dca218a6b43b6370eebbab20d > ------------------ original commit in Linus's tree ------------------ > > From a4e17d65dafdd3513042d8f00404c9b6068a825c Mon Sep 17 00:00:00 2001 > From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@xxxxxxxxxx> > Date: Tue, 5 Oct 2021 20:09:41 +0200 > Subject: [PATCH] PCI: aardvark: Fix PCIe Max Payload Size setting > MIME-Version: 1.0 > Content-Type: text/plain; charset=UTF-8 > Content-Transfer-Encoding: 8bit > > Change PCIe Max Payload Size setting in PCIe Device Control register to 512 > bytes to align with PCIe Link Initialization sequence as defined in Marvell > Armada 3700 Functional Specification. According to the specification, > maximal Max Payload Size supported by this device is 512 bytes. > > Without this kernel prints suspicious line: > > pci 0000:01:00.0: Upstream bridge's Max Payload Size set to 256 (was 16384, max 512) > > With this change it changes to: > > pci 0000:01:00.0: Upstream bridge's Max Payload Size set to 256 (was 512, max 512) > > Link: https://lore.kernel.org/r/20211005180952.6812-3-kabel@xxxxxxxxxx > Fixes: 8c39d710363c ("PCI: aardvark: Add Aardvark PCI host controller driver") > Signed-off-by: Pali Rohár <pali@xxxxxxxxxx> > Signed-off-by: Marek Behún <kabel@xxxxxxxxxx> > Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@xxxxxxx> > Reviewed-by: Marek Behún <kabel@xxxxxxxxxx> > Cc: stable@xxxxxxxxxxxxxxx > > diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c > index 596ebcfcc82d..884510630bae 100644 > --- a/drivers/pci/controller/pci-aardvark.c > +++ b/drivers/pci/controller/pci-aardvark.c > @@ -488,8 +488,9 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) > reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); > reg &= ~PCI_EXP_DEVCTL_RELAX_EN; > reg &= ~PCI_EXP_DEVCTL_NOSNOOP_EN; > + reg &= ~PCI_EXP_DEVCTL_PAYLOAD; > reg &= ~PCI_EXP_DEVCTL_READRQ; > - reg |= PCI_EXP_DEVCTL_PAYLOAD; /* Set max payload size */ > + reg |= PCI_EXP_DEVCTL_PAYLOAD_512B; > reg |= PCI_EXP_DEVCTL_READRQ_512B; > advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); > >
