On Wed, 3 Nov 2021 11:05:45 +0000, Mark Rutland wrote:
> Since ARMv8.0 the upper 32 bits of ESR_ELx have been RES0, and recently
> some of the upper bits gained a meaning and can be non-zero. For
> example, when FEAT_LS64 is implemented, ESR_ELx[36:32] contain ISS2,
> which for an ST64BV or ST64BV0 can be non-zero. This can be seen in ARM
> DDI 0487G.b, page D13-3145, section D13.2.37.
>
> Generally, we must not rely on RES0 bit remaining zero in future, and
> when extracting ESR_ELx.EC we must mask out all other bits.
>
> [...]
Applied to next, thanks!
[1/1] arm64/kvm: extract ESR_ELx.EC only
commit: 8bb084119f1acc2ec55ea085a97231e3ddb30782
Cheers,
M.
--
Without deviation from the norm, progress is not possible.
