The following commit has been merged into the x86/urgent branch of tip: Commit-ID: b2381acd3fd9bacd2c63f53b2c610c89959b31cc Gitweb: https://git.kernel.org/tip/b2381acd3fd9bacd2c63f53b2c610c89959b31cc Author: Borislav Petkov <bp@xxxxxxx> AuthorDate: Fri, 15 Oct 2021 12:46:25 +02:00 Committer: Borislav Petkov <bp@xxxxxxx> CommitterDate: Sat, 16 Oct 2021 12:37:50 +02:00 x86/fpu: Mask out the invalid MXCSR bits properly This is a fix for the fix (yeah, /facepalm). The correct mask to use is not the negation of the MXCSR_MASK but the actual mask which contains the supported bits in the MXCSR register. Reported and debugged by Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> Fixes: d298b03506d3 ("x86/fpu: Restore the masking out of reserved MXCSR bits") Signed-off-by: Borislav Petkov <bp@xxxxxxx> Tested-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> Tested-by: Ser Olmy <ser.olmy@xxxxxxxxxxxxxx> Cc: <stable@xxxxxxxxxxxxxxx> Link: https://lore.kernel.org/r/YWgYIYXLriayyezv@xxxxxxxxx --- arch/x86/kernel/fpu/signal.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kernel/fpu/signal.c b/arch/x86/kernel/fpu/signal.c index fa17a27..831b25c 100644 --- a/arch/x86/kernel/fpu/signal.c +++ b/arch/x86/kernel/fpu/signal.c @@ -385,7 +385,7 @@ static int __fpu_restore_sig(void __user *buf, void __user *buf_fx, return -EINVAL; } else { /* Mask invalid bits out for historical reasons (broken hardware). */ - fpu->state.fxsave.mxcsr &= ~mxcsr_feature_mask; + fpu->state.fxsave.mxcsr &= mxcsr_feature_mask; } /* Enforce XFEATURE_MASK_FPSSE when XSAVE is enabled */
