On Mon, Oct 11, 2021 at 11:15:16AM -0700, Florian Fainelli wrote:
> commit d88fd1b546ff19c8040cfaea76bf16aed1c5a0bb upstream
>
> When EEE support was added to the 28nm EPHY it was assumed that it would
> be able to support the standard clause 45 over clause 22 register access
> method. It turns out that the PHY does not support that, which is the
> very reason for using the indirect shadow mode 2 bank 3 access method.
>
> Implement {read,write}_mmd to allow the standard PHY library routines
> pertaining to EEE querying and configuration to work correctly on these
> PHYs. This forces us to implement a __phy_set_clr_bits() function that
> does not grab the MDIO bus lock since the PHY driver's {read,write}_mmd
> functions are always called with that lock held.
>
> Fixes: 83ee102a6998 ("net: phy: bcm7xxx: add support for 28nm EPHY")
> [florian: adjust locking since phy_{read,write}_mmd are called with no
> PHYLIB locks held]
> Signed-off-by: Florian Fainelli <f.fainelli@xxxxxxxxx>
> Signed-off-by: David S. Miller <davem@xxxxxxxxxxxxx>
> ---
> drivers/net/phy/bcm7xxx.c | 94 +++++++++++++++++++++++++++++++++++++++
> 1 file changed, 94 insertions(+)
All 3 now queued up, thanks!
greg k-h
