On Sat, Oct 02, 2021 at 01:01:31AM +0300, Ville Syrjälä wrote: > On Fri, Oct 01, 2021 at 02:08:15PM -0700, Matt Roper wrote: > > On Thu, Sep 30, 2021 at 10:09:42PM +0300, Ville Syrjala wrote: > > > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > > > > > Looks like skl/bxt/derivatives also need the plane stride > > > stretch w/a when using async flips and VT-d is enabled, or > > > else we get corruption on screen. To my surprise this was > > > even documented in bspec, but only as a note on the > > > CHICHKEN_PIPESL register description rather than on the > > > w/a list. > > > > > > So very much the same thing as on HSW/BDW, except the bits > > > moved yet again. > > > > Bspec 7522 doesn't say anything about this requirement being tied to > > VT-d on these platforms. Should we drop the intel_vtd_active() > > condition to be safe? > > I think it's just an oversight in bspec. I read through the hsd and > IIRC it did specify that it's VT-d only. Also real life confirms > it. No problems whatsoever when VT-d is disabled. BTW I was hopeful this would fix shard-skl but no such luck. Well, in fact it does fix the crc error, indicating the patch does work. Unfortunately those systems have yet another undiagnosed async flip problem. From the ci report on this series I can see that the machine was only capable of ~1.2 async flips per frame during the crc test. I guess technically anything >1 counts as "some async flips did happen" but it really should not be that low (I put the arbitrary limit in the test at two flips per frame). My cfl can do IIRC 50-150 per frame, depending on the phase of the moon and whatnot. -- Ville Syrjälä Intel
