Hi Geert, Mark, RMK, everyone, Thanks for your efforts. Let me just chime in with a few details and a question. On Fri, Sep 10, 2021 at 10:19 PM Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote: > On Fri, Sep 10, 2021 at 12:23 PM Marc Zyngier <maz@xxxxxxxxxx> wrote: > > On Thu, 09 Sep 2021 16:22:01 +0100, > > Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote: > GIC: enabling workaround for broken byte access Indeed, byte access is unsupported according to the EMEV2 documentation. The EMEV2 documentation R19UH0036EJ0600 Chapter 7 Interrupt Control on page 97 says: "Interrupt registers can be accessed via the APB bus, in 32-bit units" "For details about register functions, see ARM Generic Interrupt Controller Architecture Specification Architecture version 1.0" The file "R19UH0036EJ0600_1Chip.pdf" is the 6th edition version published in 2010 and is not marked as confidential. >From my basic research, "ARM Generic Interrupt Controller Architecture Specification Architecture version 1.0" is documented in ARM IHI 0048A from 2008 (Non-Confidential) which contains: "All GIC registers are 32-bit wide." and "All registers support 32-bit word access..." "In addition, the following registers support byte accesses:" "ICDIPR" "ICDIPTR" So the GICv1 documentation says byte access is partially supported however EMEV2 documentation says 32-bit access is required. > > + .compatible = "arm,pl390", > > + .init = gic_enable_rmw_access, > > + }, May I ask about a clarification about the EMEV2 DTS and DT binding documentation in: arch/arm/boot/dts/emev2.dts Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml On EMEV2 the DT compatible string currently seems to be the rather generic "arm,pl390". In the DT binding documentation GICv1 is listed in an example as "arm,cortex-a9-gic". Is there any reason for not using the GICv1 compatible string (and 32-bit access) for EMEV2? Just curious. Cheers, / magnus
