[ submitted for reference. The problem has now been fixed in the upstream kernel ]
Affected upstream kernel releases: v5.14-rc3, v5.14-rc4
Various stable releases with the problematic commit are also affected.
The SPI interface on systems with various Mediatek CPUs is not operational.
The problem affects all Chromebooks with Mediatek CPU since those Chromebooks
use the SPI interface to connect to the Embedded Controller.
Bisect suggests that commit 3a70dd2d050 ("spi: mediatek: fix fifo rx mode")
introduced the problem. The problem was fixed with upstream commit 0d5c3954b35e
("spi: mediatek: Fix fifo transfer").
Detailed problem description from commit 0d5c3954b35e:
Commit 3a70dd2d0503 ("spi: mediatek: fix fifo rx mode") claims that
fifo RX mode was never handled, and adds the presumably missing code
to the FIFO transfer function. However, the claim that receive data
was not handled is incorrect. It was handled as part of interrupt
handling after the transfer was complete. The code added with the above
mentioned commit reads data from the receive FIFO before the transfer
is started, which is wrong. This results in an actual transfer error
on a Hayato Chromebook.
Remove the code trying to handle receive data before the transfer is
started to fix the problem.
Guenter
