Quoting Dinh Nguyen (2021-07-13 07:46:19)
> The psi_ref_clk comes from the C2 node of the main_pll and periph_pll,
> not the C3.
>
> Fixes: 80c6b7a0894f ("clk: socfpga: agilex: add clock driver for the Agilex platform")
> Cc: stable@xxxxxxxxxxxxxxx
> Signed-off-by: Kris Chaplin <kris.chaplin@xxxxxxxxx>
> Signed-off-by: Dinh Nguyen <dinguyen@xxxxxxxxxx>
> ---
Applied to clk-next
