Re: [PATCHv3 2/4] clk: agilex/stratix10: fix bypass representation

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Quoting Dinh Nguyen (2021-06-10 19:51:59)
> Each of these clocks(s2f_usr0/1, sdmmc_clk, gpio_db, emac_ptp,
> emac0/1/2) have a bypass setting that can use the boot_clk. The
> previous representation was not correct.
> 
> Fix the representation.
> 
> Fixes: 80c6b7a0894f ("clk: socfpga: agilex: add clock driver for the Agilex platform")
> Cc: stable@xxxxxxxxxxxxxxx
> Signed-off-by: Dinh Nguyen <dinguyen@xxxxxxxxxx>
> ---

Applied to clk-next




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