The following commit has been merged into the timers/core branch of tip: Commit-ID: 8b33dfe0ba1c84c1aab2456590b38195837f1e6e Gitweb: https://git.kernel.org/tip/8b33dfe0ba1c84c1aab2456590b38195837f1e6e Author: Samuel Holland <samuel@xxxxxxxxxxxx> AuthorDate: Fri, 14 May 2021 21:14:39 -05:00 Committer: Daniel Lezcano <daniel.lezcano@xxxxxxxxxx> CommitterDate: Wed, 16 Jun 2021 17:33:04 +02:00 clocksource/arm_arch_timer: Improve Allwinner A64 timer workaround Bad counter reads are experienced sometimes when bit 10 or greater rolls over. Originally, testing showed that at least 10 lower bits would be set to the same value during these bad reads. However, some users still reported time skips. Wider testing revealed that on some chips, occasionally only the lowest 9 bits would read as the anomalous value. During these reads (which still happen only when bit 10), bit 9 would read as the correct value. Reduce the mask by one bit to cover these cases as well. Cc: stable@xxxxxxxxxxxxxxx Fixes: c950ca8c35ee ("clocksource/drivers/arch_timer: Workaround for Allwinner A64 timer instability") Reported-by: Roman Stratiienko <r.stratiienko@xxxxxxxxx> Signed-off-by: Samuel Holland <samuel@xxxxxxxxxxxx> Signed-off-by: Daniel Lezcano <daniel.lezcano@xxxxxxxxxx> Link: https://lore.kernel.org/r/20210515021439.55316-1-samuel@xxxxxxxxxxxx --- drivers/clocksource/arm_arch_timer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index 89a9e05..be6d741 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -364,7 +364,7 @@ static u64 notrace arm64_858921_read_cntvct_el0(void) do { \ _val = read_sysreg(reg); \ _retries--; \ - } while (((_val + 1) & GENMASK(9, 0)) <= 1 && _retries); \ + } while (((_val + 1) & GENMASK(8, 0)) <= 1 && _retries); \ \ WARN_ON_ONCE(!_retries); \ _val; \
