On 6/17/21 8:16 AM, Mathieu Desnoyers wrote: > ----- On Jun 15, 2021, at 11:21 PM, Andy Lutomirski luto@xxxxxxxxxx wrote: > > [...] > >> +# An architecture that wants to support >> +# MEMBARRIER_CMD_PRIVATE_EXPEDITED_SYNC_CORE needs to define precisely what it >> +# is supposed to do and implement membarrier_sync_core_before_usermode() to >> +# make it do that. Then it can select ARCH_HAS_MEMBARRIER_SYNC_CORE via >> +# Kconfig.Unfortunately, MEMBARRIER_CMD_PRIVATE_EXPEDITED_SYNC_CORE is not a >> +# fantastic API and may not make sense on all architectures. Once an >> +# architecture meets these requirements, > > Can we please remove the editorial comment about the quality of the membarrier > sync-core's API ? Done >> +# >> +# On x86, a program can safely modify code, issue >> +# MEMBARRIER_CMD_PRIVATE_EXPEDITED_SYNC_CORE, and then execute that code, via >> +# the modified address or an alias, from any thread in the calling process. >> +# >> +# On arm64, a program can modify code, flush the icache as needed, and issue >> +# MEMBARRIER_CMD_PRIVATE_EXPEDITED_SYNC_CORE to force a "context synchronizing >> +# event", aka pipeline flush on all CPUs that might run the calling process. >> +# Then the program can execute the modified code as long as it is executed >> +# from an address consistent with the icache flush and the CPU's cache type. >> +# >> +# On powerpc, a program can use MEMBARRIER_CMD_PRIVATE_EXPEDITED_SYNC_CORE >> +# similarly to arm64. It would be nice if the powerpc maintainers could >> +# add a more clear explanantion. > > We should document the requirements on ARMv7 as well. Done. > > Thanks, > > Mathieu >
