Quoting Dinh Nguyen (2021-06-09 12:17:36)
> If the bypass_reg is set, then we can return the bypass parent, however,
> if there is not a bypass_reg, we need to figure what the correct parent
> mux is.
>
> The previous code never handled the parent mux if there was a
> bypass_reg.
>
> Fixes: 80c6b7a0894f ("clk: socfpga: agilex: add clock driver for the Agilex platform")
> Cc: stable@xxxxxxxxxxxxxxx
> Signed-off-by: Dinh Nguyen <dinguyen@xxxxxxxxxx>
> ---
> drivers/clk/socfpga/clk-periph-s10.c | 9 +++++++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/socfpga/clk-periph-s10.c b/drivers/clk/socfpga/clk-periph-s10.c
> index e5a5fef76df7..e2aad5d37611 100644
> --- a/drivers/clk/socfpga/clk-periph-s10.c
> +++ b/drivers/clk/socfpga/clk-periph-s10.c
> @@ -66,14 +66,19 @@ static u8 clk_periclk_get_parent(struct clk_hw *hwclk)
> u32 clk_src, mask;
> u8 parent;
>
> + /* handle the bypass first */
> if (socfpgaclk->bypass_reg) {
> mask = (0x1 << socfpgaclk->bypass_shift);
> parent = ((readl(socfpgaclk->bypass_reg) & mask) >>
> socfpgaclk->bypass_shift);
> - } else {
> + if (parent)
> + return parent;
> + }
> +
This seems to cause a smatch warning
drivers/clk/socfpga/clk-periph-s10.c:83 clk_periclk_get_parent() error: uninitialized symbol 'parent'.
> + if (socfpgaclk->hw.reg) {
> clk_src = readl(socfpgaclk->hw.reg);
> parent = (clk_src >> CLK_MGR_FREE_SHIFT) &
> - CLK_MGR_FREE_MASK;
> + CLK_MGR_FREE_MASK;
> }
> return parent;
> }
