From: Vignesh Raghavendra <vigneshr@xxxxxx>
[ Upstream commit 52ae30f55a2a40cff549fac95de82f25403bd387 ]
Traffic through main NAVSS interconnect is coherent wrt ARM caches on
J7200 SoC. Add missing dma-coherent property to main_navss node.
Also add dma-ranges to be consistent with mcu_navss node
and with AM65/J721e main_navss and mcu_navss nodes.
Fixes: d361ed88455fe ("arm64: dts: ti: Add support for J7200 SoC")
Signed-off-by: Vignesh Raghavendra <vigneshr@xxxxxx>
Reviewed-by: Peter Ujfalusi <peter.ujfalusi@xxxxxxxxx>
Signed-off-by: Nishanth Menon <nm@xxxxxx>
Link: https://lore.kernel.org/r/20210510180601.19458-1-vigneshr@xxxxxx
Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>
---
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
index 72d6496e88dd..689538244392 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -78,6 +78,8 @@
#size-cells = <2>;
ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
ti,sci-dev-id = <199>;
+ dma-coherent;
+ dma-ranges;
main_navss_intr: interrupt-controller1 {
compatible = "ti,sci-intr";
--
2.30.2
