This looks ok to me now. As a note to the people in AMD who came up with this scheme: having to shut down the controller every time s2i is entered not only generally uses more power than using power states, but also means every time s2i is entered the SSD needs to write to the media, which causes massive endurance shortfalls. On Tue, May 18, 2021 at 10:24:33AM +0800, Prike Liang wrote: > Those patch series can handle NVMe can't suspend to D3 during s2idle > entry on some AMD platform. In this case, can be settld by assigning and > passing a PCIe bus flag to the armed device which need NVMe shutdown opt > in s2idle suspend and then use PCIe power setting to put the NVMe device > to D3. > > Prike Liang (2): > PCI: add AMD PCIe quirk for nvme shutdown opt > nvme-pci: add AMD PCIe quirk for simple suspend/resume > > drivers/nvme/host/pci.c | 2 ++ > drivers/pci/probe.c | 5 ++++- > drivers/pci/quirks.c | 7 +++++++ > include/linux/pci.h | 2 ++ > 4 files changed, 15 insertions(+), 1 deletion(-) > > -- > 2.7.4 ---end quoted text---
