On 4/20/2021 1:13 PM, Pavel Machek wrote:
Hi!
Current code blindly writes over the SWERR and the OVERFLOW bits. Write
back the bits actually read instead so the driver avoids clobbering the
OVERFLOW bit that comes after the register is read.
I believe this is incorrect. Changelog explains that we need to
preserve bits in the register...
The code is correct, but I guess maybe badly explained by me. The
IDXD_SWERR_ACK mask is IDXD_SWERR_VALID | IDXD_SWERR_OVERFLOW. When we
do write 1 to clear, we want to AND the register value that was read
with the mask so that we don't blindly clear the overflow bit under the
scenario where we read the register and then another error comes in and
set the overflow bit while we are in the interrupt handler.
diff --git a/drivers/dma/idxd/irq.c b/drivers/dma/idxd/irq.c
index a60ca11a5784..f1463fc58112 100644
--- a/drivers/dma/idxd/irq.c
+++ b/drivers/dma/idxd/irq.c
@@ -124,7 +124,9 @@ static int process_misc_interrupts(struct idxd_device *idxd, u32 cause)
for (i = 0; i < 4; i++)
idxd->sw_err.bits[i] = ioread64(idxd->reg_base +
IDXD_SWERR_OFFSET + i * sizeof(u64));
- iowrite64(IDXD_SWERR_ACK, idxd->reg_base + IDXD_SWERR_OFFSET);
+
+ iowrite64(idxd->sw_err.bits[0] & IDXD_SWERR_ACK,
+ idxd->reg_base + IDXD_SWERR_OFFSET);
...but that is not what the code does.
I suspect it should be
+ iowrite64(idxd->sw_err.bits[0] | IDXD_SWERR_ACK,
+ idxd->reg_base + IDXD_SWERR_OFFSET);
Best regards,
Pavel
