On Tue, Apr 20, 2021 at 10:48:33AM +0800, Bingbu Cao wrote: > Intel IPU(Image Processing Unit) has its own (IO)MMU hardware, > The IPU driver allocates its own page table that is not mapped > via the DMA, and thus the Intel IOMMU driver blocks access giving > this error: > > DMAR: DRHD: handling fault status reg 3 > DMAR: [DMA Read] Request device [00:05.0] PASID ffffffff > fault addr 76406000 [fault reason 06] PTE Read access is not set > > As IPU is not an external facing device which is not risky, so use > IOMMU passthrough mode for Intel IPUs. I'm wondering if IPU MMU should be described properly in the DMAR table. -- With Best Regards, Andy Shevchenko
