[AMD Public Use]
> From: Keith Busch <kbusch@xxxxxxxxxx>
> Sent: Thursday, April 15, 2021 12:24 AM
> To: Liang, Prike <Prike.Liang@xxxxxxx>
> Cc: linux-nvme@xxxxxxxxxxxxxxxxxxx; Chaitanya.Kulkarni@xxxxxxx;
> gregkh@xxxxxxxxxxxxxxxxxxx; hch@xxxxxxxxxxxxx; stable@xxxxxxxxxxxxxxx; S-
> k, Shyam-sundar <Shyam-sundar.S-k@xxxxxxx>; Deucher, Alexander
> <Alexander.Deucher@xxxxxxx>
> Subject: Re: [PATCH 2/2] nvme-pci: add AMD PCIe quirk for suspend/resume
>
> On Wed, Apr 14, 2021 at 04:18:01PM +0800, Prike Liang wrote:
> > The NVME device pluged in some AMD PCIE root port will resume timeout
> > from s2idle which caused by NVME power CFG lost in the SMU FW restore.
> > This issue can be workaround by using PCIe power set with simple
> > suspend/resume process path instead of APST. In the onwards ASIC will
> > try do the NVME shutdown save and restore in the BIOS and still need
> > PCIe power setting to resume from RTD3 for s2idle.
> >
> > Update the nvme_acpi_storage_d3() _with previously added quirk.
> >
> > Signed-off-by: Chaitanya Kulkarni <chaitanya.kulkarni@xxxxxxx>
> > [ck: split patches for nvme and pcie]
>
> Chaitanya's Sign-off should be under the annotation explaining what he
> changed, and placed below the original author's sign-off.
>
> > Signed-off-by: Prike Liang <Prike.Liang@xxxxxxx>
> > Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@xxxxxxx>
> > Reviewed-by: Chaitanya Kulkarni <chaitanya.kulkarni@xxxxxxx>
> > Cc: <stable@xxxxxxxxxxxxxxx> # 5.11+
> > ---
>
> It doesn't appear that you're reading Greg's autobot reply. This spot right
> here is where you should describe what is different about this patch
> compared to your previous versions.
>
Thanks proposal and will update the author info and patch version.
> > drivers/nvme/host/pci.c | 7 +++++++
> > 1 file changed, 7 insertions(+)
> >
> > diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c index
> > 6bad4d4..ce9f42b 100644
> > --- a/drivers/nvme/host/pci.c
> > +++ b/drivers/nvme/host/pci.c
> > @@ -2832,6 +2832,7 @@ static bool nvme_acpi_storage_d3(struct pci_dev
> > *dev) {
> > struct acpi_device *adev;
> > struct pci_dev *root;
> > +struct pci_dev *rdev;
> > acpi_handle handle;
> > acpi_status status;
> > u8 val;
> > @@ -2845,6 +2846,12 @@ static bool nvme_acpi_storage_d3(struct
> pci_dev *dev)
> > if (!root)
> > return false;
> >
> > +rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));
>
> Instead of assuming '0', shouldn't you use the domain of the NVMe PCI
> device?
Now we just add the NVMe shutdown quirk by checking the root complex ID instead of adding more and more variables endpoint NVMe device.
