Re: [PATCH v7 RESEND] MIPS: force use FR=0 or FRE for FPXX binaries

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Thomas Bogendoerfer <tsbogend@xxxxxxxxxxxxxxxx> 于2021年3月15日周一 下午11:00写道:
>
> On Fri, Mar 12, 2021 at 10:48:59AM +0000, YunQiang Su wrote:
> > The MIPS FPU may have 3 mode:
> >   FR=0: MIPS I style, all of the FPR are single.
> >   FR=1: all 32 FPR can be double.
> >   FRE: redirecting the rw of odd-FPR to the upper 32bit of even-double FPR.
> >
> > The binary may have 3 mode:
> >   FP32: can only work with FR=0 and FRE mode
> >   FPXX: can work with all of FR=0/FR=1/FRE mode.
> >   FP64: can only work with FR=1 mode
> >
> > Some binary, for example the output of golang, may be mark as FPXX,
> > while in fact they are FP32. It is caused by the bug of design and linker:
> >   Object produced by pure Go has no FP annotation while in fact they are FP32;
> >   if we link them with the C module which marked as FPXX,
> >   the result will be marked as FPXX. If these fake-FPXX binaries is executed
> >   in FR=1 mode, some problem will happen.
> >
> > In Golang, now we add the FP32 annotation, so the future golang programs
> > won't have this problem. While for the existing binaries, we need a
> > kernel workaround.
>
> what about just rebuilding them ? They are broken, so why should we fix
> broken user binaries with kernel hacks ?
>

In fact without O32_FP64_SUPPORT option is enabled, the FP=0 mode is
always used for FPXX.
In fact it doesn't change the behaviour of kernel.

> > Currently, FR=1 mode is used for all FPXX binary, it makes some wrong
> > behivour of the binaries. Since FPXX binary can work with both FR=1 and FR=0,
> > we force it to use FR=0 or FRE (for R6 CPU).
>
> I'm not sure, if I want to take this patch.
>

In fact, I'd prefer to use a config option to control this behivour.

> Maciej, what's your take on this ?
>
> Thomas.
>
> --
> Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
> good idea.                                                [ RFC1925, 2.3 ]



-- 
YunQiang Su




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