On Thu, Mar 18, 2021 at 08:00:10PM +0200, Ville Syrjälä wrote:
> On Wed, Mar 17, 2021 at 08:49:01PM +0200, Imre Deak wrote:
> > By the specification the 0xF0000 - 0xF02FF range is only valid if the
> > LTTPR revision at 0xF0000 is at least 1.4. Disable the LTTPR support
> > otherwise.
> >
> > Fixes: 7b2a4ab8b0ef ("drm/i915: Switch to LTTPR transparent mode link training")
> > Cc: <stable@xxxxxxxxxxxxxxx> # v5.11
> > Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> > Signed-off-by: Imre Deak <imre.deak@xxxxxxxxx>
> > ---
> > .../gpu/drm/i915/display/intel_dp_link_training.c | 14 ++++++++++----
> > 1 file changed, 10 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > index d8d90903226f..d92eb192c89d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > @@ -100,17 +100,23 @@ static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp)
> > return false;
> >
> > if (drm_dp_read_lttpr_common_caps(&intel_dp->aux,
> > - intel_dp->lttpr_common_caps) < 0) {
> > - intel_dp_reset_lttpr_common_caps(intel_dp);
> > - return false;
> > - }
> > + intel_dp->lttpr_common_caps) < 0)
> > + goto reset_caps;
>
> BTW just noticed this oddball thing in the spec:
> "DPTX shall read specific registers within the LTTPR field (DPCD
> Addresses F0000h through F0004h; see Table 2-198) to determine
> whether any LTTPR(s) are present and if so, how many. This read
> shall be in the form of a 5-byte native AUX Read transaction."
>
> Why exactly 5 bytes? I have no idea. Doesn't really make sense.
> Just wondering if we really need to respect that and some LTTPRs
> would fsck things up if we read more...
I pointed this out to spec people and the new version (2.1) will require
this to be 8 bytes. But yes, I do hope no existing ones depend on this
being 5 bytes.
> Anyways
> Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> >
> > drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
> > "LTTPR common capabilities: %*ph\n",
> > (int)sizeof(intel_dp->lttpr_common_caps),
> > intel_dp->lttpr_common_caps);
> >
> > + /* The minimum value of LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV is 1.4 */
> > + if (intel_dp->lttpr_common_caps[0] < 0x14)
> > + goto reset_caps;
> > +
> > return true;
> > +
> > +reset_caps:
> > + intel_dp_reset_lttpr_common_caps(intel_dp);
> > + return false;
> > }
> >
> > static bool
> > --
> > 2.25.1
>
> --
> Ville Syrjälä
> Intel
