On Sat, Mar 06, 2021 at 08:17:24PM -0800, Ilya Lipnitskiy wrote: > Upstream a long-standing OpenWrt patch [0] that fixes MT7620 PCIe PLL > lock check. The existing code checks the wrong register bit: PPLL_SW_SET > is not defined in PPLL_CFG1 and bit 31 of PPLL_CFG1 is marked as reserved > in the MT7620 Programming Guide. The correct bit to check for PLL lock > is PPLL_LD (bit 23). > > Also reword the error message for clarity. > > Without this change it is unlikely that this driver ever worked with > mainline kernel. > > [0]: https://lists.infradead.org/pipermail/lede-commits/2017-July/004441.html > > Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@xxxxxxxxx> > Cc: John Crispin <john@xxxxxxxxxxx> > Cc: linux-mips@xxxxxxxxxxxxxxx > Cc: linux-mediatek@xxxxxxxxxxxxxxxxxxx > Cc: linux-kernel@xxxxxxxxxxxxxxx > Cc: stable@xxxxxxxxxxxxxxx > --- > arch/mips/pci/pci-mt7620.c | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) applied to mips-next. Thomas. -- Crap can work. Given enough thrust pigs will fly, but it's not necessarily a good idea. [ RFC1925, 2.3 ]
