On Mon, Dec 28, 2020 at 12:32 PM Mathieu Desnoyers <mathieu.desnoyers@xxxxxxxxxxxx> wrote: > > ----- On Dec 28, 2020, at 2:44 PM, Andy Lutomirski luto@xxxxxxxxxx wrote: > > > On Mon, Dec 28, 2020 at 11:09 AM Russell King - ARM Linux admin > > <linux@xxxxxxxxxxxxxxx> wrote: > >> > >> On Mon, Dec 28, 2020 at 07:29:34PM +0100, Jann Horn wrote: > >> > After chatting with rmk about this (but without claiming that any of > >> > this is his opinion), based on the manpage, I think membarrier() > >> > currently doesn't really claim to be synchronizing caches? It just > >> > serializes cores. So arguably if userspace wants to use membarrier() > >> > to synchronize code changes, userspace should first do the code > >> > change, then flush icache as appropriate for the architecture, and > >> > then do the membarrier() to ensure that the old code is unused? > > ^ exactly, yes. > > >> > > >> > For 32-bit arm, rmk pointed out that that would be the cacheflush() > >> > syscall. That might cause you to end up with two IPIs instead of one > >> > in total, but we probably don't care _that_ much about extra IPIs on > >> > 32-bit arm? > > This was the original thinking, yes. The cacheflush IPI will flush specific > regions of code, and the membarrier IPI issues context synchronizing > instructions. > > Architectures with coherent i/d caches don't need the cacheflush step. There are different levels of coherency -- VIVT architectures may have differing requirements compared to PIPT, etc. In any case, I feel like the approach taken by the documentation is fundamentally confusing. Architectures don't all speak the same language How about something like: The SYNC_CORE operation causes all threads in the caller's address space (including the caller) to execute an architecture-defined barrier operation. membarrier() will ensure that this barrier is executed at a time such that all data writes done by the calling thread before membarrier() are made visible by the barrier. Additional architecture-dependent cache management operations may be required to use this for JIT code. x86: SYNC_CORE executes a barrier that will cause subsequent instruction fetches to observe prior writes. Currently this will be a "serializing" instruction, but, if future improved CPU documentation becomes available and relaxes this requirement, the barrier may change. The kernel guarantees that writing new or modified instructions to normal memory (and issuing SFENCE if the writes were non-temporal) then doing a membarrier SYNC_CORE operation is sufficient to cause all threads in the caller's address space to execute the new or modified instructions. This is true regardless of whether or not those instructions are written at the same virtual address from which they are subsequently executed. No additional cache management is required on x86. arm: Something about the cache management syscalls. arm64: Ditto powerpc: I have no idea.
