On Thu, Nov 26, 2020 at 02:08:41PM +0000, Chris Wilson wrote: > Ville noticed that the last mocs entry is used unconditionally by the HW > when it performs cache evictions, and noted that while the value is not > meant to be writable by the driver, we should program it to a reasonable > value nevertheless. > > As it turns out, we can change the value of mocs:63 and the value we > were programming into it would cause hard hangs in conjunction with > atomic operations. > > v2: Add details from bspec about how it is used by HW > > Suggested-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2707 > Fixes: 3bbaba0ceaa2 ("drm/i915: Added Programming of the MOCS") > Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > Cc: Jason Ekstrand <jason@xxxxxxxxxxxxxx> > Cc: <stable@xxxxxxxxxxxxxxx> # v4.3+ > --- > drivers/gpu/drm/i915/gt/intel_mocs.c | 14 +++++++++++++- > 1 file changed, 13 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c > index 254873e1646e..26cedde80476 100644 > --- a/drivers/gpu/drm/i915/gt/intel_mocs.c > +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c > @@ -131,7 +131,19 @@ static const struct drm_i915_mocs_entry skl_mocs_table[] = { > GEN9_MOCS_ENTRIES, > MOCS_ENTRY(I915_MOCS_CACHED, > LE_3_WB | LE_TC_2_LLC_ELLC | LE_LRUM(3), > - L3_3_WB) > + L3_3_WB), > + > + /* > + * mocs:63 > + * - used by the L3 for all its evictions. > + * Thus it is expected to allow LLC cacheability to enable coherent > + * flows to be maintained. > + * - used to force L3 uncachable cycles. > + * Thus it is expected to make the surce L3 uncacheable. "surce"? > + */ > + MOCS_ENTRY(63, > + LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_1_UC) > }; > > /* NOTE: the LE_TGT_CACHE is not used on Broxton */ > -- > 2.20.1 -- Ville Syrjälä Intel
