This is a note to let you know that I've just added the patch titled
sparc64: Make sure %pil interrupts are enabled during hypervisor yield.
to the 3.10-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
sparc64-make-sure-pil-interrupts-are-enabled-during-hypervisor-yield.patch
and it can be found in the queue-3.10 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.
>From foo@baz Sun Apr 20 18:23:45 PDT 2014
From: "David S. Miller" <davem@xxxxxxxxxxxxx>
Date: Mon, 24 Mar 2014 14:45:12 -0400
Subject: sparc64: Make sure %pil interrupts are enabled during hypervisor yield.
From: "David S. Miller" <davem@xxxxxxxxxxxxx>
[ Upstream commit cb3042d609e30e6144024801c89be3925106752b ]
In arch_cpu_idle() we must enable %pil based interrupts before
potentially invoking the hypervisor cpu yield call.
As per the Hypervisor API documentation for cpu_yield:
Interrupts which are blocked by some mechanism other that
pstate.ie (for example %pil) are not guaranteed to cause
a return from this service.
It seems that only first generation Niagara chips are hit by this
bug. My best guess is that later chips implement this in hardware
and wake up anyways from %pil events, whereas in first generation
chips the yield is implemented completely in hypervisor code and
requires %pil to be enabled in order to wake properly from this
call.
Fixes: 87fa05aeb3a5 ("sparc: Use generic idle loop")
Reported-by: Fabio M. Di Nitto <fabbione@xxxxxxxxxxxx>
Reported-by: Jan Engelhardt <jengelh@xxxxxxx>
Tested-by: Jan Engelhardt <jengelh@xxxxxxx>
Signed-off-by: David S. Miller <davem@xxxxxxxxxxxxx>
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
arch/sparc/kernel/process_64.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
--- a/arch/sparc/kernel/process_64.c
+++ b/arch/sparc/kernel/process_64.c
@@ -57,9 +57,12 @@ void arch_cpu_idle(void)
{
if (tlb_type != hypervisor) {
touch_nmi_watchdog();
+ local_irq_enable();
} else {
unsigned long pstate;
+ local_irq_enable();
+
/* The sun4v sleeping code requires that we have PSTATE.IE cleared over
* the cpu sleep hypervisor call.
*/
@@ -81,7 +84,6 @@ void arch_cpu_idle(void)
: "=&r" (pstate)
: "i" (PSTATE_IE));
}
- local_irq_enable();
}
#ifdef CONFIG_HOTPLUG_CPU
Patches currently in stable-queue which might be from davem@xxxxxxxxxxxxx are
queue-3.10/sparc-pci-fix-incorrect-address-calculation-of-pci-bridge-windows-on-simba-bridges.patch
queue-3.10/sparc64-don-t-treat-64-bit-syscall-return-codes-as-32-bit.patch
queue-3.10/sparc32-fix-build-failure-for-arch_jump_label_transform.patch
queue-3.10/revert-sparc64-fix-__copy_-to-from-_user_inatomic-defines.patch
queue-3.10/sparc64-make-sure-pil-interrupts-are-enabled-during-hypervisor-yield.patch
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