On Fri, Nov 20, 2020 at 10:22:45AM +1100, Daniel Axtens wrote: > IBM Power9 processors can speculatively operate on data in the L1 > cache before it has been completely validated, via a way-prediction > mechanism. It is not possible for an attacker to determine the > contents of impermissible memory using this method, since these > systems implement a combination of hardware and software security > measures to prevent scenarios where protected data could be leaked. > > However these measures don't address the scenario where an attacker > induces the operating system to speculatively execute instructions > using data that the attacker controls. This can be used for example to > speculatively bypass "kernel user access prevention" techniques, as > discovered by Anthony Steinhauser of Google's Safeside Project. This > is not an attack by itself, but there is a possibility it could be > used in conjunction with side-channels or other weaknesses in the > privileged code to construct an attack. > > This issue can be mitigated by flushing the L1 cache between privilege > boundaries of concern. This series flushes the cache on kernel entry and > after kernel user accesses. > > Thanks to Nick Piggin, Russell Currey, Christopher M. Riedl, Michael > Ellerman and Spoorthy S for their work in developing, optimising, > testing and backporting these fixes, and to the many others who helped > behind the scenes. All of these for all branches are now queued up, thanks for making them so easy to apply! greg k-h
