3.4-stable review patch. If anyone has any objections, please let me know. ------------------ From: Sergei Ianovich <ynvich@xxxxxxxxx> commit ff88b4724fde18056a4c539f7327389aec0f4c2d upstream. Erratum 71 of PXA270M Processor Family Specification Update (April 19, 2010) explains that watchdog reset time is just 8us insead of 10ms in EMTS. If SDRAM is not reset, it causes memory bus congestion and the device hangs. We put SDRAM in selfresh mode before watchdog reset, removing potential freezes. Without this patch PXA270-based ICP DAS LP-8x4x hangs after up to 40 reboots. With this patch it has successfully rebooted 500 times. Signed-off-by: Sergei Ianovich <ynvich@xxxxxxxxx> Tested-by: Marek Vasut <marex@xxxxxxx> Signed-off-by: Haojian Zhuang <haojian.zhuang@xxxxxxxxx> Signed-off-by: Olof Johansson <olof@xxxxxxxxx> [bwh: Backported to 3.2: adjust context] Signed-off-by: Ben Hutchings <ben@xxxxxxxxxxxxxxx> Cc: Yang Yingliang <yangyingliang@xxxxxxxxxx> Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx> --- arch/arm/mach-pxa/reset.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) --- a/arch/arm/mach-pxa/reset.c +++ b/arch/arm/mach-pxa/reset.c @@ -13,6 +13,7 @@ #include <mach/regs-ost.h> #include <mach/reset.h> +#include <mach/smemc.h> unsigned int reset_status; EXPORT_SYMBOL(reset_status); @@ -80,6 +81,12 @@ static void do_hw_reset(void) OWER = OWER_WME; OSSR = OSSR_M3; OSMR3 = OSCR + 368640; /* ... in 100 ms */ + /* + * SDRAM hangs on watchdog reset on Marvell PXA270 (erratum 71) + * we put SDRAM into self-refresh to prevent that + */ + while (1) + writel_relaxed(MDREFR_SLFRSH, MDREFR); } void pxa_restart(char mode, const char *cmd) @@ -103,4 +110,3 @@ void pxa_restart(char mode, const char * break; } } - -- To unsubscribe from this list: send the line "unsubscribe stable" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html