From: Marek Szyprowski <m.szyprowski@xxxxxxxxxxx> commit 0212a0483b0a36cc94cfab882b3edbb41fcfe1cd upstream. BPLL clock must not be disabled because it is needed for proper DRAM operation. This is normally handled by respective memory devfreq driver, but when that driver is not yet probed or its probe has been deferred the clock might get disabled what causes board hang. Fix this by calling clk_prepare_enable() directly from the clock provider driver. Cc: stable@xxxxxxxxxxxxxxx Signed-off-by: Marek Szyprowski <m.szyprowski@xxxxxxxxxxx> Reviewed-by: Lukasz Luba <lukasz.luba@xxxxxxx> Tested-by: Lukasz Luba <lukasz.luba@xxxxxxx> Acked-by: Krzysztof Kozlowski <krzk@xxxxxxxxxx> Link: https://lore.kernel.org/r/20200807133143.22748-1-m.szyprowski@xxxxxxxxxxx Fixes: 6e7674c3c6df ("memory: Add DMC driver for Exynos5422") Signed-off-by: Sylwester Nawrocki <s.nawrocki@xxxxxxxxxxx> Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx> --- drivers/clk/samsung/clk-exynos5420.c | 5 +++++ 1 file changed, 5 insertions(+) --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -1655,6 +1655,11 @@ static void __init exynos5x_clk_init(str * main G3D clock enablement status. */ clk_prepare_enable(__clk_lookup("mout_sw_aclk_g3d")); + /* + * Keep top BPLL mux enabled permanently to ensure that DRAM operates + * properly. + */ + clk_prepare_enable(__clk_lookup("mout_bpll")); samsung_clk_of_add_provider(np, ctx); }
