From: Eddie James <eajames@xxxxxxxxxxxxx> commit ebd4050c6144b38098d8eed34df461e5e3fa82a9 upstream. When calculating the clock divider, start dividing at 2 instead of 1. The divider is divided by two at the end of the calculation, so starting at 1 may result in a divider of 0, which shouldn't happen. Signed-off-by: Eddie James <eajames@xxxxxxxxxxxxx> Reviewed-by: Andrew Jeffery <andrew@xxxxxxxx> Acked-by: Joel Stanley <joel@xxxxxxxxx> Acked-by: Adrian Hunter <adrian.hunter@xxxxxxxxx> Link: https://lore.kernel.org/r/20200709195706.12741-3-eajames@xxxxxxxxxxxxx Cc: stable@xxxxxxxxxxxxxxx # v5.4+ Signed-off-by: Ulf Hansson <ulf.hansson@xxxxxxxxxx> Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx> --- drivers/mmc/host/sdhci-of-aspeed.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- a/drivers/mmc/host/sdhci-of-aspeed.c +++ b/drivers/mmc/host/sdhci-of-aspeed.c @@ -68,7 +68,7 @@ static void aspeed_sdhci_set_clock(struc if (WARN_ON(clock > host->max_clk)) clock = host->max_clk; - for (div = 1; div < 256; div *= 2) { + for (div = 2; div < 256; div *= 2) { if ((parent / div) <= clock) break; }
