On Tue, Jul 07, 2020 at 04:37:41PM +0100, Marc Zyngier wrote:
> Commit 005c34ae4b44f085120d7f371121ec7ded677761 upstream.
>
> The GIC driver uses a RMW sequence to update the affinity, and
> relies on the gic_lock_irqsave/gic_unlock_irqrestore sequences
> to update it atomically.
>
> But these sequences only expand into anything meaningful if
> the BL_SWITCHER option is selected, which almost never happens.
>
> It also turns out that using a RMW and locks is just as silly,
> as the GIC distributor supports byte accesses for the GICD_TARGETRn
> registers, which when used make the update atomic by definition.
>
> Drop the terminally broken code and replace it by a byte write.
>
> Fixes: 04c8b0f82c7d ("irqchip/gic: Make locking a BL_SWITCHER only feature")
> Cc: stable@xxxxxxxxxxxxxxx
> Signed-off-by: Marc Zyngier <maz@xxxxxxxxxx>
> ---
> drivers/irqchip/irq-gic.c | 13 +++----------
> 1 file changed, 3 insertions(+), 10 deletions(-)
Thanks for the backport, now queued up.
greg k-h
