On 03/06/2014 02:39 PM, Stefan Richter wrote:
Since commit bd972688eb24
"firewire: ohci: Fix 'failed to read phy reg' on FW643 rev8",
there is a high chance that firewire-ohci fails to initialize LSI née
Agere controllers.
https://bugzilla.kernel.org/show_bug.cgi?id=65151
Peter Hurley points out the reason: IEEE 1394a:2000 clause 5A.1 (or
IEEE 1394:2008 clause 17.2.1) say: "The PHY shall insure that no more
than 10 ms elapse from the reassertion of LPS until the interface is
reset. The link shall not assert LReq until the reset is complete."
In other words, the link needs to give the PHY at least 10 ms to get
the interface operational.
With just the msleep(1) in bd972688eb24, the first read_phy_reg()
during ohci_enable() may happen before the phy-link interface reset was
finished, and fail. Due to the high variability of msleep(n) with small
n, this failure was not fully reproducible, and not apparent at all with
low CONFIG_HZ setting.
On the other hand, Peter can no longer reproduce the issue with FW643
rev8. The read phy reg failures that happened back then may have had an
unrelated cause. So, just revert bd972688eb24, except for the valid
comment on TSB82AA2 cards.
With patch applied, happened last night but I just noticed this am:
Mar 12 20:47:40 thor kernel: [ 2.516017] firewire_ohci 0000:01:00.0: failed to read phy reg 1
Mar 12 20:47:40 thor kernel: [ 2.516043] CPU: 2 PID: 62 Comm: kworker/2:1 Not tainted 3.14.0-rc1+fwconsole-xeon #rc1+fwconsole
Mar 12 20:47:40 thor kernel: [ 2.516055] Hardware name: Dell Inc. Precision WorkStation T5400 /0RW203, BIOS A11 04/30/2012
Mar 12 20:47:40 thor kernel: [ 2.516077] Workqueue: firewire br_work [firewire_core]
Mar 12 20:47:40 thor kernel: [ 2.516088] ffff8802af718000 ffff8802b3231d48 ffffffff81704b05 0000000000000001
Mar 12 20:47:40 thor kernel: [ 2.516112] 0000000000000067 ffff8802b3231d78 ffffffffa003bb69 ffff8802b3231da8
Mar 12 20:47:40 thor kernel: [ 2.516127] ffff8802af718630 ffff8802af718000 0000000000000001 ffff8802b3231da8
Mar 12 20:47:40 thor kernel: [ 2.516142] Call Trace:
Mar 12 20:47:40 thor kernel: [ 2.516154] [<ffffffff81704b05>] dump_stack+0x4f/0x7c
Mar 12 20:47:40 thor kernel: [ 2.516165] [<ffffffffa003bb69>] read_phy_reg+0x89/0xd0 [firewire_ohci]
Mar 12 20:47:40 thor kernel: [ 2.516175] [<ffffffffa003bcd9>] ohci_read_phy_reg+0x39/0x60 [firewire_ohci]
Mar 12 20:47:40 thor kernel: [ 2.516187] [<ffffffffa000f30f>] fw_send_phy_config+0xbf/0xe0 [firewire_core]
Mar 12 20:47:40 thor kernel: [ 2.516198] [<ffffffffa000752c>] br_work+0x6c/0xe0 [firewire_core]
Mar 12 20:47:40 thor kernel: [ 2.516209] [<ffffffff8106975f>] process_one_work+0x16f/0x440
Mar 12 20:47:40 thor kernel: [ 2.516217] [<ffffffff81069ea2>] worker_thread+0x122/0x380
Mar 12 20:47:40 thor kernel: [ 2.516225] [<ffffffff81069d80>] ? rescuer_thread+0x310/0x310
Mar 12 20:47:40 thor kernel: [ 2.516234] [<ffffffff81071119>] kthread+0xc9/0xe0
Mar 12 20:47:40 thor kernel: [ 2.516242] [<ffffffff81700000>] ? pcpu_dump_alloc_info+0x154/0x271
Mar 12 20:47:40 thor kernel: [ 2.516251] [<ffffffff81071050>] ? flush_kthread_worker+0x80/0x80
Mar 12 20:47:40 thor kernel: [ 2.516261] [<ffffffff8171812c>] ret_from_fork+0x7c/0xb0
Mar 12 20:47:40 thor kernel: [ 2.516269] [<ffffffff81071050>] ? flush_kthread_worker+0x80/0x80
....
Mar 12 20:47:40 thor kernel: [ 3.316012] firewire_ohci 0000:01:00.0: failed to read phy reg 5
Mar 12 20:47:40 thor kernel: [ 3.316027] CPU: 2 PID: 62 Comm: kworker/2:1 Not tainted 3.14.0-rc1+fwconsole-xeon #rc1+fwconsole
Mar 12 20:47:40 thor kernel: [ 3.316365] Hardware name: Dell Inc. Precision WorkStation T5400 /0RW203, BIOS A11 04/30/2012
Mar 12 20:47:40 thor kernel: [ 3.316643] Workqueue: firewire br_work [firewire_core]
Mar 12 20:47:40 thor kernel: [ 3.317009] ffff8802af718000 ffff8802b3231d38 ffffffff81704b05 0000000000000001
Mar 12 20:47:40 thor kernel: [ 3.317485] 0000000000000067 ffff8802b3231d68 ffffffffa003bb69 ffff8802b3231d78
Mar 12 20:47:40 thor kernel: [ 3.317970] 0000000000000005 ffff8802af718000 0000000000000000 ffff8802b3231d98
Mar 12 20:47:40 thor kernel: [ 3.318452] Call Trace:
Mar 12 20:47:40 thor kernel: [ 3.318934] [<ffffffff81704b05>] dump_stack+0x4f/0x7c
Mar 12 20:47:40 thor kernel: [ 3.319427] [<ffffffffa003bb69>] read_phy_reg+0x89/0xd0 [firewire_ohci]
Mar 12 20:47:40 thor kernel: [ 3.319922] [<ffffffffa003bbdd>] update_phy_reg+0x2d/0x70 [firewire_ohci]
Mar 12 20:47:40 thor kernel: [ 3.320426] [<ffffffffa003bc6d>] ohci_update_phy_reg+0x4d/0x80 [firewire_ohci]
Mar 12 20:47:40 thor kernel: [ 3.320927] [<ffffffffa000754f>] br_work+0x8f/0xe0 [firewire_core]
Mar 12 20:47:40 thor kernel: [ 3.321434] [<ffffffff8106975f>] process_one_work+0x16f/0x440
Mar 12 20:47:40 thor kernel: [ 3.321940] [<ffffffff81069ea2>] worker_thread+0x122/0x380
Mar 12 20:47:40 thor kernel: [ 3.322444] [<ffffffff81069d80>] ? rescuer_thread+0x310/0x310
Mar 12 20:47:40 thor kernel: [ 3.322940] [<ffffffff81071119>] kthread+0xc9/0xe0
Mar 12 20:47:40 thor kernel: [ 3.323433] [<ffffffff81700000>] ? pcpu_dump_alloc_info+0x154/0x271
Mar 12 20:47:40 thor kernel: [ 3.323924] [<ffffffff81071050>] ? flush_kthread_worker+0x80/0x80
Mar 12 20:47:40 thor kernel: [ 3.324417] [<ffffffff8171812c>] ret_from_fork+0x7c/0xb0
Mar 12 20:47:40 thor kernel: [ 3.324901] [<ffffffff81071050>] ? flush_kthread_worker+0x80/0x80
Reported-by: Mikhail Gavrilov
Reported-by: Jay Fenlason <fenlason@xxxxxxxxxx>
Reported-by: Clemens Ladisch <clemens@xxxxxxxxxx>
Reported-by: Peter Hurley <peter@xxxxxxxxxxxxxxxxxx>
Cc: stable@xxxxxxxxxxxxxxx # v3.10+
Signed-off-by: Stefan Richter <stefanr@xxxxxxxxxxxxxxxxx>
---
drivers/firewire/ohci.c | 15 ++-------------
1 file changed, 2 insertions(+), 13 deletions(-)
--- a/drivers/firewire/ohci.c
+++ b/drivers/firewire/ohci.c
@@ -290,7 +290,6 @@ static char ohci_driver_name[] = KBUILD_
#define QUIRK_NO_MSI 0x10
#define QUIRK_TI_SLLZ059 0x20
#define QUIRK_IR_WAKE 0x40
-#define QUIRK_PHY_LCTRL_TIMEOUT 0x80
/* In case of multiple matches in ohci_quirks[], only the first one is used. */
static const struct {
@@ -303,10 +302,7 @@ static const struct {
QUIRK_BE_HEADERS},
{PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6,
- QUIRK_PHY_LCTRL_TIMEOUT | QUIRK_NO_MSI},
-
- {PCI_VENDOR_ID_ATT, PCI_ANY_ID, PCI_ANY_ID,
- QUIRK_PHY_LCTRL_TIMEOUT},
+ QUIRK_NO_MSI},
{PCI_VENDOR_ID_CREATIVE, PCI_DEVICE_ID_CREATIVE_SB1394, PCI_ANY_ID,
QUIRK_RESET_PACKET},
@@ -353,7 +349,6 @@ MODULE_PARM_DESC(quirks, "Chip quirks (d
", disable MSI = " __stringify(QUIRK_NO_MSI)
", TI SLLZ059 erratum = " __stringify(QUIRK_TI_SLLZ059)
", IR wake unreliable = " __stringify(QUIRK_IR_WAKE)
- ", phy LCtrl timeout = " __stringify(QUIRK_PHY_LCTRL_TIMEOUT)
")");
#define OHCI_PARAM_DEBUG_AT_AR 1
@@ -2299,9 +2294,6 @@ static int ohci_enable(struct fw_card *c
* TI TSB82AA2 + TSB81BA3(A) cards signal LPS enabled early but
* cannot actually use the phy at that time. These need tens of
* millisecods pause between LPS write and first phy access too.
- *
- * But do not wait for 50msec on Agere/LSI cards. Their phy
- * arbitration state machine may time out during such a long wait.
*/
reg_write(ohci, OHCI1394_HCControlSet,
@@ -2309,11 +2301,8 @@ static int ohci_enable(struct fw_card *c
OHCI1394_HCControl_postedWriteEnable);
flush_writes(ohci);
- if (!(ohci->quirks & QUIRK_PHY_LCTRL_TIMEOUT))
+ for (lps = 0, i = 0; !lps && i < 3; i++) {
msleep(50);
-
- for (lps = 0, i = 0; !lps && i < 150; i++) {
- msleep(1);
lps = reg_read(ohci, OHCI1394_HCControlSet) &
OHCI1394_HCControl_LPS;
}
--
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