On Thu, Apr 16, 2020 at 07:06:41PM -0700, Brian Norris wrote:
> If you just read the last sentence from Michal, you get the wrong
> picture. There's no hard-coding of gpiochipX numbers going on. We only
> had the pin offsets "hardcoded" (in ACPI), and the kernel driver
> unilaterally changed from a contiguous mapping to a non-contiguous
> mapping.
OK, I now understand the issue. My apologies that I was not able to
figure that out from the previous explanation.
So indeed if relative GPIO numbering inside the gpiochip was changed
then it is kernel regression and needs to be dealt with.
> How do you recommend determining (both pre- and
> post-commit-03c4749dd6c7ff94) whether pin 22 is at offset 22, vs. offset
> 19?
I wonder if we can add back the previous GPIO base like this?
diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c
index 4c74fdde576d..f53de56bb763 100644
--- a/drivers/pinctrl/intel/pinctrl-cherryview.c
+++ b/drivers/pinctrl/intel/pinctrl-cherryview.c
@@ -1591,17 +1591,18 @@ static int chv_gpio_add_pin_ranges(struct gpio_chip *chip)
struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
const struct chv_community *community = pctrl->community;
const struct chv_gpio_pinrange *range;
- int ret, i;
+ int ret, i, offset;
- for (i = 0; i < community->ngpio_ranges; i++) {
+ for (i = 0, offset = 0; i < community->ngpio_ranges; i++) {
range = &community->gpio_ranges[i];
- ret = gpiochip_add_pin_range(chip, dev_name(pctrl->dev),
- range->base, range->base,
- range->npins);
+ ret = gpiochip_add_pin_range(chip, dev_name(pctrl->dev), offset,
+ range->base, range->npins);
if (ret) {
dev_err(pctrl->dev, "failed to add GPIO pin range\n");
return ret;
}
+
+ offset += range->npins;
}
return 0;
