This is a note to let you know that I've just added the patch titled
drm/i915: Prevent MI_DISPLAY_FLIP straddling two cachelines on IVB
to the 3.13-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
drm-i915-prevent-mi_display_flip-straddling-two-cachelines-on-ivb.patch
and it can be found in the queue-3.13 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.
>From f66fab8e1cd6b3127ba4c5c0d11539fbe1de1e36 Mon Sep 17 00:00:00 2001
From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Date: Tue, 11 Feb 2014 19:52:06 +0200
Subject: drm/i915: Prevent MI_DISPLAY_FLIP straddling two cachelines on IVB
MIME-Version: 1.0
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From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
commit f66fab8e1cd6b3127ba4c5c0d11539fbe1de1e36 upstream.
According to BSpec the entire MI_DISPLAY_FLIP packet must be contained
in a single cacheline. Make sure that happens.
v2: Use intel_ring_begin_cacheline_safe()
v3: Use intel_ring_cacheline_align() (Chris)
Cc: Bjoern C <lkml@xxxxxxxxxxxx>
Cc: Alexandru DAMIAN <alexandru.damian@xxxxxxxxx>
Cc: Enrico Tagliavini <enrico.tagliavini@xxxxxxxxx>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=74053
Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Cc: stable@xxxxxxxxxxxxxxx
Signed-off-by: Daniel Vetter <daniel.vetter@xxxxxxxx>
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
drivers/gpu/drm/i915/intel_display.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8335,6 +8335,20 @@ static int intel_gen7_queue_flip(struct
if (ring->id == RCS)
len += 6;
+ /*
+ * BSpec MI_DISPLAY_FLIP for IVB:
+ * "The full packet must be contained within the same cache line."
+ *
+ * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
+ * cacheline, if we ever start emitting more commands before
+ * the MI_DISPLAY_FLIP we may need to first emit everything else,
+ * then do the cacheline alignment, and finally emit the
+ * MI_DISPLAY_FLIP.
+ */
+ ret = intel_ring_cacheline_align(ring);
+ if (ret)
+ goto err_unpin;
+
ret = intel_ring_begin(ring, len);
if (ret)
goto err_unpin;
Patches currently in stable-queue which might be from ville.syrjala@xxxxxxxxxxxxxxx are
queue-3.13/drm-i915-add-intel_ring_cachline_align.patch
queue-3.13/drm-i915-prevent-mi_display_flip-straddling-two-cachelines-on-ivb.patch
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