On Thu, Jan 30, 2020 at 12:52:55PM +0100, Hans de Goede wrote: > This does not matter though, we can model the chain of PLLs as a single > PLL with a quotient equal to the quotients of all PLLs in the chain > multiplied. > > So we can create a simplified model of the CPU clock setup using a > reference clock of 100 MHz plus a quotient which gets us as close to the > frequency from the DSM as possible. s/DSM/SDM/ ? > For the 83.3 MHz example from above this would give us 100 MHz * 5 / 6 = > 83 and 1/3 MHz, which matches exactly what has been measured on actual hw. > > This commit makes the tsc_msr.c code use a simplified PLL model with a > reference clock of 100 MHz for all Bay and Cherry Trail models. > + * Bay Trail SDM MSR_FSB_FREQ frequencies simplified PLL model: > + * 000: 100 * 5 / 6 = 83.3333 MHz > + * 001: 100 * 1 / 1 = 100.0000 MHz > + * 010: 100 * 4 / 3 = 133.3333 MHz > + * 011: 100 * 7 / 6 = 116.6667 MHz > + * 100: 100 * 4 / 5 = 80.0000 MHz > + * Cherry Trail SDM MSR_FSB_FREQ frequencies simplified PLL model: > + * 0000: 100 * 5 / 6 = 83.3333 MHz > + * 0001: 100 * 1 / 1 = 100.0000 MHz > + * 0010: 100 * 4 / 3 = 133.3333 MHz > + * 0011: 100 * 7 / 6 = 116.6667 MHz > + * 0100: 100 * 4 / 5 = 80.0000 MHz > + * 0101: 100 * 14 / 15 = 93.3333 MHz > + * 0110: 100 * 9 / 10 = 90.0000 MHz > + * 0111: 100 * 8 / 9 = 88.8889 MHz > + * 1000: 100 * 7 / 8 = 87.5000 MHz > + * Merriefield (BYT MID) SDM MSR_FSB_FREQ frequencies simplified PLL model: > + * 0001: 100 * 1 / 1 = 100.0000 MHz > + * 0010: 100 * 4 / 3 = 133.3333 MHz > + * Moorefield (CHT MID) SDM MSR_FSB_FREQ frequencies simplified PLL model: > + * 0000: 100 * 5 / 6 = 83.3333 MHz > + * 0001: 100 * 1 / 1 = 100.0000 MHz > + * 0010: 100 * 4 / 3 = 133.3333 MHz > + * 0011: 100 * 1 / 1 = 100.0000 MHz Unless I'm going cross-eyed, that's 4 times the exact same table. Do we want to use the Cherry Trail table (for being the most complete) for all of them?
