On Fri, Jan 24, 2020 at 09:16:58AM -0500, Sasha Levin wrote:
> From: Lubomir Rintel <lkundrak@xxxxx>
>
> [ Upstream commit 8bea5ac0fbc5b2103f8779ddff216122e3c2e1ad ]
>
> Determined empirically, no documentation is available.
>
> The OLPC XO-1.75 laptop used parent 1, that one being VCTCXO/4 (65MHz), but
> thought it's a VCTCXO/2 (130MHz). The mmp2 timer driver, not knowing
> what is going on, ended up just dividing the rate as of
> commit f36797ee4380 ("ARM: mmp/mmp2: dt: enable the clock")'
Hi,
this has to go together with this one (in other stable trees too):
commit 0bd0f30bbf060891f58866a46083a9931f71787c
Author: Lubomir Rintel <lkundrak@xxxxx>
Date: Wed Dec 18 20:04:53 2019 +0100
ARM: mmp: do not divide the clock rate
This was done because the clock driver returned the wrong rate, which is
fixed in "clk: mmp2: Fix the order of timer mux parents" patch.
It removes a workaround for the same issue from before it was
understood what is going on. If it stays, the clock will run twice as
fast.
Thanks
Lubo
>
> Link: https://lore.kernel.org/r/20191218190454.420358-3-lkundrak@xxxxx
> Signed-off-by: Lubomir Rintel <lkundrak@xxxxx>
> Acked-by: Stephen Boyd <sboyd@xxxxxxxxxx>
> Signed-off-by: Olof Johansson <olof@xxxxxxxxx>
> Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>
> ---
> drivers/clk/mmp/clk-of-mmp2.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/mmp/clk-of-mmp2.c b/drivers/clk/mmp/clk-of-mmp2.c
> index a60a1be937ad6..b4a95cbbda989 100644
> --- a/drivers/clk/mmp/clk-of-mmp2.c
> +++ b/drivers/clk/mmp/clk-of-mmp2.c
> @@ -134,7 +134,7 @@ static DEFINE_SPINLOCK(ssp3_lock);
> static const char *ssp_parent_names[] = {"vctcxo_4", "vctcxo_2", "vctcxo", "pll1_16"};
>
> static DEFINE_SPINLOCK(timer_lock);
> -static const char *timer_parent_names[] = {"clk32", "vctcxo_2", "vctcxo_4", "vctcxo"};
> +static const char *timer_parent_names[] = {"clk32", "vctcxo_4", "vctcxo_2", "vctcxo"};
>
> static DEFINE_SPINLOCK(reset_lock);
>
> --
> 2.20.1
>
