From: Vipul Kumar <vipul_kumar@xxxxxxxxxx>
commit f3a02ecebed7 ("x86/tsc: Set TSC_KNOWN_FREQ and TSC_RELIABLE
flags on Intel Atom SoCs"), is setting TSC_KNOWN_FREQ and TSC_RELIABLE
flags for Soc's which is causing time drift on Valleyview/Bay trail Soc.
This patch introduces a new macro to skip these flags.
Signed-off-by: Vipul Kumar <vipul_kumar@xxxxxxxxxx>
Cc: stable@xxxxxxxxxxxxxxx
---
Changes in V2:
- Added linux-stable along with kernel version in CC
Changes in V3:
- Intead of cpuid-level, used macro to skip the flags
Tested-on: SIEMENS-IPC227E board
---
arch/x86/Kconfig | 10 ++++++++++
arch/x86/kernel/tsc_msr.c | 4 ++++
2 files changed, 14 insertions(+)
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 5e89499..f6c175d 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -1155,6 +1155,16 @@ config X86_THERMAL_VECTOR
def_bool y
depends on X86_MCE_INTEL
+config X86_FEATURE_TSC_UNKNOWN_FREQ
+ bool "Support to skip tsc known frequency flag"
+ help
+ Include support to skip X86_FEATURE_TSC_KNOWN_FREQ flag
+
+ X86_FEATURE_TSC_KNOWN_FREQ flag is causing time-drift on Valleyview/
+ Baytrail SoC.
+ By selecting this option, user can skip X86_FEATURE_TSC_KNOWN_FREQ
+ flag to use refine tsc freq calibration.
+
source "arch/x86/events/Kconfig"
config X86_LEGACY_VM86
diff --git a/arch/x86/kernel/tsc_msr.c b/arch/x86/kernel/tsc_msr.c
index e0cbe4f..60c3a4a 100644
--- a/arch/x86/kernel/tsc_msr.c
+++ b/arch/x86/kernel/tsc_msr.c
@@ -112,6 +112,10 @@ unsigned long cpu_khz_from_msr(void)
lapic_timer_period = (freq * 1000) / HZ;
#endif
+#ifdef CONFIG_X86_FEATURE_TSC_UNKNOWN_FREQ
+ return res;
+#endif
+
/*
* TSC frequency determined by MSR is always considered "known"
* because it is reported by HW.
--
1.9.1
