Hello Shimoda-san, hi Geert, hi Sergei,
On Wed, Oct 30, 2019 at 08:27:04PM +0900, Yoshihiro Shimoda wrote:
> According to the R-Car Gen2/3 manual, "Be sure to write the initial
> value (= H'80FF 0000) to MACCTLR before enabling PCIETCTLR.CFINIT."
> To avoid unexpected behaviors, this patch fixes it.
>
> Fixes: c25da4778803 ("PCI: rcar: Add Renesas R-Car PCIe driver")
> Fixes: be20bbcb0a8c ("PCI: rcar: Add the initialization of PCIe link in resume_noirq()")
> Cc: <stable@xxxxxxxxxxxxxxx> # v5.2+
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx>
> ---
> drivers/pci/controller/pcie-rcar.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/pci/controller/pcie-rcar.c b/drivers/pci/controller/pcie-rcar.c
> index 40d8c54..d470ab8 100644
> --- a/drivers/pci/controller/pcie-rcar.c
> +++ b/drivers/pci/controller/pcie-rcar.c
> @@ -91,6 +91,7 @@
> #define LINK_SPEED_2_5GTS (1 << 16)
> #define LINK_SPEED_5_0GTS (2 << 16)
> #define MACCTLR 0x011058
> +#define MACCTLR_INIT_VAL 0x80ff0000
Actually, I do believe there is an inconsistency in the manual,
since the following statements pretty much contradict one another:
1. (as quoted by Shimoda-san from "Initial Setting of PCI Express")
> Be sure to write the initial value (= H'80FF 0000) to MACCTLR
> before enabling PCIETCTLR.CFINIT.
2. Description of SPCHG bit in "54.2.98 MAC Control Register (MACCTLR)"
> Only writing 1 is valid and writing 0 is invalid.
The last "invalid" sounds like "bad things can happen" aka "expect
undefined behaviors" when SPCHG is written "0".
While leaving the decision on the patch inclusion to the maintainers, I
hope, in the long run, Renesas can resolve the documentation conflict
with the HW team and the tech writers.
> #define SPEED_CHANGE BIT(24)
> #define SCRAMBLE_DISABLE BIT(27)
> #define PMSR 0x01105c
> @@ -613,6 +614,8 @@ static int rcar_pcie_hw_init(struct rcar_pcie *pcie)
> if (IS_ENABLED(CONFIG_PCI_MSI))
> rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR);
>
> + rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR);
> +
> /* Finish initialization - establish a PCI Express link */
> rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR);
>
> @@ -1235,6 +1238,7 @@ static int rcar_pcie_resume_noirq(struct device *dev)
> return 0;
>
> /* Re-establish the PCIe link */
> + rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR);
> rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR);
> return rcar_pcie_wait_for_dl(pcie);
> }
--
Best Regards,
Eugeniu
