On Thu, Sep 19, 2019 at 10:32:47PM +0200, Greg KH wrote:
> On Mon, Sep 09, 2019 at 02:45:01PM +0200, Niklas Cassel wrote:
> > Hello,
> >
> > I would like to request
> > 2a355ec25729 ("arm64: kpti: Whitelist Cortex-A CPUs that don't implement the CSV3 field")
> >
> > to be backported to 4.19 stable.
> >
> > These CPUs are not susceptible to Meltdown, so enabling the mitigations
> > for Meltdown (kpti) should be redundant, especially since we know that
> > it can have a huge performance penalty for certain workloads.
> >
> > kpti will still be automatically enabled if KASLR is enabled.
>
> Now queued up, thanks.
>
Hello Greg, Will,
How about applying this also to v4.14 stable?
(Since kpti is also enabled on Cortex-A CPUs in v4.14.)
2a355ec25729 does not apply cleanly on v4.14.y,
since a LOT of things have changed in the file.
git log --oneline 2a355ec25729053bb9a1a89b6c1d1cdd6c3b3fb1 --not linux-stable/linux-4.14.y arch/arm64/kernel/cpufeature.c | wc -l
72
However, I've attached a simple backport of the commit.
Kind regards,
Niklas
>From 84406bca325ad4dc1c5d517801d298ae8c9b68a0 Mon Sep 17 00:00:00 2001
From: Will Deacon <will.deacon@xxxxxxx>
Date: Thu, 13 Dec 2018 13:47:38 +0000
Subject: [PATCH] arm64: kpti: Whitelist Cortex-A CPUs that don't implement the
CSV3 field
commit 2a355ec25729053bb9a1a89b6c1d1cdd6c3b3fb1 upstream.
While the CSV3 field of the ID_AA64_PFR0 CPU ID register can be checked
to see if a CPU is susceptible to Meltdown and therefore requires kpti
to be enabled, existing CPUs do not implement this field.
We therefore whitelist all unaffected Cortex-A CPUs that do not implement
the CSV3 field.
Signed-off-by: Will Deacon <will.deacon@xxxxxxx>
Signed-off-by: Niklas Cassel <niklas.cassel@xxxxxxxxxx>
---
MIDR_CORTEX_A35 is not included, since the define does not exist in v4.14.y.
arch/arm64/kernel/cpufeature.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 3312d46fa29e..57ec681a8f11 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -838,6 +838,11 @@ static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
switch (read_cpuid_id() & MIDR_CPU_MODEL_MASK) {
case MIDR_CAVIUM_THUNDERX2:
case MIDR_BRCM_VULCAN:
+ case MIDR_CORTEX_A53:
+ case MIDR_CORTEX_A55:
+ case MIDR_CORTEX_A57:
+ case MIDR_CORTEX_A72:
+ case MIDR_CORTEX_A73:
return false;
}
--
2.21.0
