On Thursday, August 22, 2019 10:32:00 AM CEST Jarkko Nikula wrote:
> My assumption in the commit b53548f9d9e4 ("spi: pxa2xx: Remove LPSS private
> register restoring during resume") that Intel Lynxpoint and compatible
> based chipsets may not need LPSS private registers saving and restoring
> over suspend/resume cycle turned out to be false on Intel Broadwell.
>
> Curtis Malainey sent a patch bringing above change back and reported the
> LPSS SPI Chip Select control was lost over suspend/resume cycle on
> Broadwell machine.
>
> Instead of reverting above commit lets add LPSS private register
> saving/restoring also for all LPSS SPI, I2C and UART controllers on
> Lynxpoint and compatible chipset to make sure context is not lost in
> case nothing else preserves it like firmware or if LPSS is always on.
>
> Fixes: b53548f9d9e4 ("spi: pxa2xx: Remove LPSS private register restoring during resume")
> Reported-by: Curtis Malainey <cujomalainey@xxxxxxxxxxxx>
> Cc: <stable@xxxxxxxxxxxxxxx>
> Signed-off-by: Jarkko Nikula <jarkko.nikula@xxxxxxxxxxxxxxx>
> ---
> drivers/acpi/acpi_lpss.c | 8 +++++---
> 1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/acpi/acpi_lpss.c b/drivers/acpi/acpi_lpss.c
> index d696f165a50e..60bbc5090abe 100644
> --- a/drivers/acpi/acpi_lpss.c
> +++ b/drivers/acpi/acpi_lpss.c
> @@ -219,12 +219,13 @@ static void bsw_pwm_setup(struct lpss_private_data *pdata)
> }
>
> static const struct lpss_device_desc lpt_dev_desc = {
> - .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR,
> + .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR
> + | LPSS_SAVE_CTX,
> .prv_offset = 0x800,
> };
>
> static const struct lpss_device_desc lpt_i2c_dev_desc = {
> - .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_LTR,
> + .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_LTR | LPSS_SAVE_CTX,
> .prv_offset = 0x800,
> };
>
> @@ -236,7 +237,8 @@ static struct property_entry uart_properties[] = {
> };
>
> static const struct lpss_device_desc lpt_uart_dev_desc = {
> - .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR,
> + .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR
> + | LPSS_SAVE_CTX,
> .clk_con_id = "baudclk",
> .prv_offset = 0x800,
> .setup = lpss_uart_setup,
>
Applied, thanks!
