Am 25.07.19 um 21:25 schrieb Sumit Saxena: > In Resize BAR control register, bits[8:12] represents size of BAR. > As per PCIe specification, below is encoded values in register bits > to actual BAR size table: > > Bits BAR size > 0 1 MB > 1 2 MB > 2 4 MB > 3 8 MB > -- > > For 1 MB BAR size, BAR size bits should be set to 0 but incorrectly > these bits are set to "1f". Latest megaraid_sas and mpt3sas adapters > which support Resizable BAR with 1 MB BAR size fails to initialize > during system resume from S3 sleep. > > Fix: Correctly calculate BAR size bits for Resize BAR control register. > > V2: > -Simplified calculation of BAR size bits as suggested by Christian Koenig. > > CC: stable@xxxxxxxxxxxxxxx # v4.16+ > Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=203939 > Fixes: d3252ace0bc652a1a244455556b6a549f969bf99 ("PCI: Restore resized BAR state on resume") > Signed-off-by: Sumit Saxena <sumit.saxena@xxxxxxxxxxxx> Reviewed-by: Christian König <christian.koenig@xxxxxxx> > --- > drivers/pci/pci.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c > index 29ed5ec1ac27..e59921296125 100644 > --- a/drivers/pci/pci.c > +++ b/drivers/pci/pci.c > @@ -1438,7 +1438,7 @@ static void pci_restore_rebar_state(struct pci_dev *pdev) > pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); > bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX; > res = pdev->resource + bar_idx; > - size = order_base_2((resource_size(res) >> 20) | 1) - 1; > + size = order_base_2(resource_size(res) >> 20); > ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE; > ctrl |= size << PCI_REBAR_CTRL_BAR_SHIFT; > pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
