Commit-ID: 2f217d58a8a086d3399fecce39fb358848e799c4 Gitweb: https://git.kernel.org/tip/2f217d58a8a086d3399fecce39fb358848e799c4 Author: Kim Phillips <kim.phillips@xxxxxxx> AuthorDate: Fri, 28 Jun 2019 21:59:33 +0000 Committer: Ingo Molnar <mingo@xxxxxxxxxx> CommitDate: Sat, 13 Jul 2019 11:21:27 +0200 perf/x86/amd/uncore: Set the thread mask for F17h L3 PMCs Fill in the L3 performance event select register ThreadMask bitfield, to enable per hardware thread accounting. Signed-off-by: Kim Phillips <kim.phillips@xxxxxxx> Signed-off-by: Peter Zijlstra (Intel) <peterz@xxxxxxxxxxxxx> Cc: <stable@xxxxxxxxxxxxxxx> Cc: Alexander Shishkin <alexander.shishkin@xxxxxxxxxxxxxxx> Cc: Arnaldo Carvalho de Melo <acme@xxxxxxxxxx> Cc: Borislav Petkov <bp@xxxxxxxxx> Cc: Gary Hook <Gary.Hook@xxxxxxx> Cc: H. Peter Anvin <hpa@xxxxxxxxx> Cc: Janakarajan Natarajan <Janakarajan.Natarajan@xxxxxxx> Cc: Jiri Olsa <jolsa@xxxxxxxxxx> Cc: Linus Torvalds <torvalds@xxxxxxxxxxxxxxxxxxxx> Cc: Martin Liska <mliska@xxxxxxx> Cc: Namhyung Kim <namhyung@xxxxxxxxxx> Cc: Peter Zijlstra <peterz@xxxxxxxxxxxxx> Cc: Pu Wen <puwen@xxxxxxxx> Cc: Stephane Eranian <eranian@xxxxxxxxxx> Cc: Suravee Suthikulpanit <Suravee.Suthikulpanit@xxxxxxx> Cc: Thomas Gleixner <tglx@xxxxxxxxxxxxx> Cc: Vince Weaver <vincent.weaver@xxxxxxxxx> Link: https://lkml.kernel.org/r/20190628215906.4276-2-kim.phillips@xxxxxxx Signed-off-by: Ingo Molnar <mingo@xxxxxxxxxx> --- arch/x86/events/amd/uncore.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c index c2c4ae5fbbfc..a6ea07f2aa84 100644 --- a/arch/x86/events/amd/uncore.c +++ b/arch/x86/events/amd/uncore.c @@ -202,15 +202,22 @@ static int amd_uncore_event_init(struct perf_event *event) hwc->config = event->attr.config & AMD64_RAW_EVENT_MASK_NB; hwc->idx = -1; + if (event->cpu < 0) + return -EINVAL; + /* * SliceMask and ThreadMask need to be set for certain L3 events in * Family 17h. For other events, the two fields do not affect the count. */ - if (l3_mask && is_llc_event(event)) - hwc->config |= (AMD64_L3_SLICE_MASK | AMD64_L3_THREAD_MASK); + if (l3_mask && is_llc_event(event)) { + int thread = 2 * (cpu_data(event->cpu).cpu_core_id % 4); - if (event->cpu < 0) - return -EINVAL; + if (smp_num_siblings > 1) + thread += cpu_data(event->cpu).apicid & 1; + + hwc->config |= (1ULL << (AMD64_L3_THREAD_SHIFT + thread) & + AMD64_L3_THREAD_MASK) | AMD64_L3_SLICE_MASK; + } uncore = event_to_amd_uncore(event); if (!uncore)
