This is a note to let you know that I've just added the patch titled
arm64: Use Normal NonCacheable memory for writecombine
to the 3.10-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
arm64-use-normal-noncacheable-memory-for-writecombine.patch
and it can be found in the queue-3.10 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.
>From 4f00130b70e5eee813cc7bc298e0f3fdf79673cc Mon Sep 17 00:00:00 2001
From: Catalin Marinas <catalin.marinas@xxxxxxx>
Date: Fri, 29 Nov 2013 10:56:14 +0000
Subject: arm64: Use Normal NonCacheable memory for writecombine
From: Catalin Marinas <catalin.marinas@xxxxxxx>
commit 4f00130b70e5eee813cc7bc298e0f3fdf79673cc upstream.
This provides better performance compared to Device GRE and also allows
unaligned accesses. Such memory is intended to be used with standard RAM
(e.g. framebuffers) and not I/O.
Signed-off-by: Catalin Marinas <catalin.marinas@xxxxxxx>
Cc: Mark Brown <broonie@xxxxxxxxxx>
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
arch/arm64/include/asm/pgtable.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -184,7 +184,7 @@ static inline void set_pte_at(struct mm_
#define pgprot_noncached(prot) \
__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE))
#define pgprot_writecombine(prot) \
- __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_GRE))
+ __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC))
#define pgprot_dmacoherent(prot) \
__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC))
#define __HAVE_PHYS_MEM_ACCESS_PROT
Patches currently in stable-queue which might be from catalin.marinas@xxxxxxx are
queue-3.10/arm64-dts-reserve-the-memory-used-for-secondary-cpu-release-address.patch
queue-3.10/arm64-only-enable-local-interrupts-after-the-cpu-is-marked-online.patch
queue-3.10/arm64-virt-ensure-visibility-of-__boot_cpu_mode.patch
queue-3.10/arm64-change-kernel-stack-size-to-16k.patch
queue-3.10/arm64-use-normal-noncacheable-memory-for-writecombine.patch
queue-3.10/arm64-fix-possible-invalid-fpsimd-initialization-state.patch
queue-3.10/arm64-check-for-number-of-arguments-in-syscall_get-set_arguments.patch
queue-3.10/arm64-remove-unused-cpu_name-ascii-in-arch-arm64-mm-proc.s.patch
queue-3.10/clocksource-arch_timer-use-virtual-counters.patch
queue-3.10/arm64-ptrace-avoid-using-hw_breakpoint_empty-for-disabled-events.patch
queue-3.10/arm64-avoid-cache-flushing-in-flush_dcache_page.patch
queue-3.10/arm64-spinlock-retry-trylock-operation-if-strex-fails-on-free-lock.patch
queue-3.10/arm64-do-not-flush-the-d-cache-for-anonymous-pages.patch
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