This is a note to let you know that I've just added the patch titled
arm64: Avoid cache flushing in flush_dcache_page()
to the 3.10-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
arm64-avoid-cache-flushing-in-flush_dcache_page.patch
and it can be found in the queue-3.10 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.
>From b5b6c9e9149d8a7c3f1d7b9d0c046c6184e1dd17 Mon Sep 17 00:00:00 2001
From: Catalin Marinas <catalin.marinas@xxxxxxx>
Date: Wed, 1 May 2013 12:23:05 +0100
Subject: arm64: Avoid cache flushing in flush_dcache_page()
From: Catalin Marinas <catalin.marinas@xxxxxxx>
commit b5b6c9e9149d8a7c3f1d7b9d0c046c6184e1dd17 upstream.
The flush_dcache_page() function is called when the kernel modified a
page cache page. Since the D-cache on AArch64 does not have aliases
this function can simply mark the page as dirty for later flushing via
set_pte_at()/__sync_icache_dcache() if the page is executable (to ensure
the I-D cache coherency).
Signed-off-by: Catalin Marinas <catalin.marinas@xxxxxxx>
Reported-by: Will Deacon <will.deacon@xxxxxxx>
Acked-by: Will Deacon <will.deacon@xxxxxxx>
Cc: Mark Brown <broonie@xxxxxxxxxx>
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
arch/arm64/mm/flush.c | 22 ++++------------------
1 file changed, 4 insertions(+), 18 deletions(-)
--- a/arch/arm64/mm/flush.c
+++ b/arch/arm64/mm/flush.c
@@ -94,28 +94,14 @@ void __sync_icache_dcache(pte_t pte, uns
}
/*
- * Ensure cache coherency between kernel mapping and userspace mapping of this
- * page.
+ * This function is called when a page has been modified by the kernel. Mark
+ * it as dirty for later flushing when mapped in user space (if executable,
+ * see __sync_icache_dcache).
*/
void flush_dcache_page(struct page *page)
{
- struct address_space *mapping;
-
- /*
- * The zero page is never written to, so never has any dirty cache
- * lines, and therefore never needs to be flushed.
- */
- if (page == ZERO_PAGE(0))
- return;
-
- mapping = page_mapping(page);
- if (mapping && mapping_mapped(mapping)) {
- __flush_dcache_page(page);
- __flush_icache_all();
- set_bit(PG_dcache_clean, &page->flags);
- } else {
+ if (test_bit(PG_dcache_clean, &page->flags))
clear_bit(PG_dcache_clean, &page->flags);
- }
}
EXPORT_SYMBOL(flush_dcache_page);
Patches currently in stable-queue which might be from catalin.marinas@xxxxxxx are
queue-3.10/arm64-dts-reserve-the-memory-used-for-secondary-cpu-release-address.patch
queue-3.10/arm64-only-enable-local-interrupts-after-the-cpu-is-marked-online.patch
queue-3.10/arm64-virt-ensure-visibility-of-__boot_cpu_mode.patch
queue-3.10/arm64-change-kernel-stack-size-to-16k.patch
queue-3.10/arm64-use-normal-noncacheable-memory-for-writecombine.patch
queue-3.10/arm64-fix-possible-invalid-fpsimd-initialization-state.patch
queue-3.10/arm64-check-for-number-of-arguments-in-syscall_get-set_arguments.patch
queue-3.10/arm64-remove-unused-cpu_name-ascii-in-arch-arm64-mm-proc.s.patch
queue-3.10/clocksource-arch_timer-use-virtual-counters.patch
queue-3.10/arm64-ptrace-avoid-using-hw_breakpoint_empty-for-disabled-events.patch
queue-3.10/arm64-avoid-cache-flushing-in-flush_dcache_page.patch
queue-3.10/arm64-spinlock-retry-trylock-operation-if-strex-fails-on-free-lock.patch
queue-3.10/arm64-do-not-flush-the-d-cache-for-anonymous-pages.patch
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