On Tue, Jun 4, 2019 at 4:24 PM Bjorn Andersson
<bjorn.andersson@xxxxxxxxxx> wrote:
>
> After issuing a PHY_START request to the QMP, the hardware documentation
> states that the software should wait for the PCS_READY_STATUS to become
> 1.
>
> With the introduction of c9b589791fc1 ("phy: qcom: Utilize UFS reset
> controller") an additional 1ms delay was introduced between the start
> request and the check of the status bit. This greatly increases the
> chances for the hardware to actually becoming ready before the status
> bit is read.
>
> The result can be seen in that UFS PHY enabling is now reported as a
> failure in 10% of the boots on SDM845, which is a clear regression from
> the previous rare/occasional failure.
>
> This patch fixes the "break condition" of the poll to check for the
> correct state of the status bit.
>
> Unfortunately PCIe on 8996 and 8998 does not specify the mask_pcs_ready
> register, which means that the code checks a bit that's always 0. So the
> patch also fixes these, in order to not regress these targets.
>
> Cc: stable@xxxxxxxxxxxxxxx
> Cc: Evan Green <evgreen@xxxxxxxxxxxx>
> Cc: Marc Gonzalez <marc.w.gonzalez@xxxxxxx>
> Cc: Vivek Gautam <vivek.gautam@xxxxxxxxxxxxxx>
> Fixes: 73d7ec899bd8 ("phy: qcom-qmp: Add msm8998 PCIe QMP PHY support")
> Fixes: e78f3d15e115 ("phy: qcom-qmp: new qmp phy driver for qcom-chipsets")
> Signed-off-by: Bjorn Andersson <bjorn.andersson@xxxxxxxxxx>
Nice find.
Reviewed-by: Evan Green <evgreen@xxxxxxxxxxxx>
